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JPS63211692A - 両面配線基板 - Google Patents

両面配線基板

Info

Publication number
JPS63211692A
JPS63211692A JP62042677A JP4267787A JPS63211692A JP S63211692 A JPS63211692 A JP S63211692A JP 62042677 A JP62042677 A JP 62042677A JP 4267787 A JP4267787 A JP 4267787A JP S63211692 A JPS63211692 A JP S63211692A
Authority
JP
Japan
Prior art keywords
plate
board
wiring
double
printed circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62042677A
Other languages
English (en)
Inventor
金沢　幸男
渡辺　昌行
利夫 管野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Japan Display Inc
Original Assignee
Hitachi Device Engineering Co Ltd
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Device Engineering Co Ltd, Hitachi Ltd filed Critical Hitachi Device Engineering Co Ltd
Priority to JP62042677A priority Critical patent/JPS63211692A/ja
Priority to KR1019880001839A priority patent/KR970003991B1/ko
Publication of JPS63211692A publication Critical patent/JPS63211692A/ja
Priority to US07/397,352 priority patent/US5095407A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/0218—Reduction of cross-talk, noise or electromagnetic interference by printed shielding conductors, ground planes or power plane
    • H05K1/0224—Patterned shielding planes, ground planes or power planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0271—Arrangements for reducing stress or warp in rigid printed circuit boards, e.g. caused by loads, vibrations or differences in thermal expansion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00011—Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/10251—Elemental semiconductors, i.e. Group IV
    • H01L2924/10253—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
    • H05K1/0253—Impedance adaptations of transmission lines by special lay-out of power planes, e.g. providing openings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0286—Programmable, customizable or modifiable circuits
    • H05K1/0287—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns
    • H05K1/0289—Programmable, customizable or modifiable circuits having an universal lay-out, e.g. pad or land grid patterns or mesh patterns having a matrix lay-out, i.e. having selectively interconnectable sets of X-conductors and Y-conductors in different planes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09336—Signal conductors in same plane as power plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/0929—Conductive planes
    • H05K2201/09345—Power and ground in the same plane; Power planes for two voltages in one plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09654—Shape and layout details of conductors covering at least two types of conductors provided for in H05K2201/09218 - H05K2201/095
    • H05K2201/09681—Mesh conductors, e.g. as a ground plane
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10159—Memory
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
    • H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は面実装用プリント基板に関し、特に、両面プリ
ント基板の改良に関する、 〔従来の技術〕 従来のＶＩＩＳプレート（電源プレート）入りのプリン
ト基板は多層基板を用い、その内層にＶＢ８プレートを
設けていた。
この内層にＶ８８プレートを有する例えば四層構造の多
層基板の構造の一例は次の通りである。
すなわち、基板の表面に表面配線を設けるとともにその
裏面にも裏面配線を設け、当該基板にスルーホールをあ
けて当該スルーホールの内部に導体をつげ、表面配線と
裏面配線を導通させ、更に、基板の内部に前記スルーホ
ール導体忙対し直角方向に第１層のＶＳＳプレートおよ
び第２層のＶ８Ｂプレートよりなる二層のＶｓ８プレー
ト（電源層）を設けて成る。
当該多層基板の製法例は、一般に、薄い樹脂板の上にパ
ターンを形成し、それらを何枚か積み重ね、加圧し、熱
を加えて樹脂を硬化させ、その後、必要な個所にドリル
で穴（スルーホール）をあげ、穴の内部に導体をつけ、
各層のパターン間の導通なはかることにより行われる。
このように、表面配線のほかに裏面配線を設けたり、そ
のために、これら配線を導通するためのスルーホールを
あけ、メッキなどにより導体を当該スルーホール内部に
つけたり、何層にもわたりＶＳＢプレートを形成した樹
脂板を積層し、加熱加圧操作を施さねばならないなどそ
の基板価格は高いものにつく。また、複数の樹脂板を積
層して所定の板厚のものとするなどその板厚管理が難し
い、また、スルーホール導体による導通の場合一般にス
ルーホールの信頼性が劣ることが多く、信頼性向上の阻
害要因であった。従来の基板ではこのスルーホールを大
量に設ける必要があり、束に、加圧に際しクラックを生
じ易いなどプレス加工性が良くないという難点がある。
なお、プリント基板について述べた文献の例としては、
（株）工業調査会発行［電子材料Ｊ１９８３年１０月ｐ
１５〜１６４、同１９８４年１０月ｐ１５〜１２８、同
１９８４年４月号ｐ１４３〜１４８があげられる。
〔発明が解決しようとする問題点〕
本発明は、かかる難点を克服した両面プリント基板を提
供することを目的とする。
本発明の前記なうびにそのほかの目的と新規な特徴は、
本明細書の記述および添付図面からあきらかになるであ
ろう。
〔問題点を解決するための手段〕
本願において開示される発明のうち代表的なものの概要
を簡単に説明すれば、下記のとおりである。
本発明では、従来、裏面に設けていた配線の大部分をフ
ァインプロセスを活用して表面に移し、また、従来、内
層に設げていたＶ８ｇプレートを裏面に移す。そして、
これＫより、ｖＢＢプレート付の両面プリント基板を構
成する。
〔作用〕
このように、裏面に設けていた配線の大部分を表面に移
したので従来のごとき表面配線と裏面配線との導通なと
るためのスルーホールの形成を大幅に減らすことができ
、更に内層Ｋ　Ｖｓｓプレートを敷設するのでないので
、従来のごとく、複数の樹脂板の上にｖａｎプレートの
パターンを形成し、積層する必要がなくなり、基板は一
枚の樹脂板により構成することもでき、生産コストが安
く、板厚管理が容易で、スルーホールを大幅に減らすこ
とができ、信頼性が向上し、製法が簡略化され、生産歩
留が向上し、裏面のＶ８Ｂプレートによりシールド効果
が奏されるなど、優れた特長を有するＶＳ８プレート付
の両面プリント基板を得ることに成功した。
〔実施例〕
次に、本発明を、図面に示す実施例に基づいて説明する
。
第１図は本発明の実施例を示す要部断面図、第２図は同
要部平面図を模式的に示す。
これら図に示すように、基板ｌの表面に表面配線２を形
成し、当該基板１の裏面ＩＩＣＶＢＢプレート３を付設
する。
基板１は、例えば樹脂基板により構成され、その用いら
れる基材と結合材との組み合せによって各種のものを構
成でき、基材としては、ガラス繊維９紙５合成繊維など
が例示され、また、結合材としては、エポキシ樹脂、フ
ェノール樹脂、ポリイミド樹脂などが例示される。樹脂
基板としては、ガラス繊維を基材とするエポキシ樹脂基
板（ガラスエポキシ基板）が好ましい。
基板ｌの表面配線２の形成は、ファインプロセスを活用
し【、従来裏面に設けられていた配線の大部分を表面に
移す形で微細配線を施す。
基板ｉのその表面への表面配線２の形成は、例えば、ガ
ラス繊維を布状に編んだものにエポキシ樹脂を含浸せし
めた後乾燥し、これらを所要厚さになる枚数（例えば１
５〜１６枚）積ね合せ、表面に銅箔をも同時に積ね合せ
た後に加熱圧着してなるガラスエポキシ銅張積層板に、
エツチング技術やホトレジスト技術を駆使して導体配線
パターン２を形成することにより行われる。
Ｖ８Ｂプレート３の形成も、前記において、銅箔を反対
側の面にも積ね合せ、同様に、エツチング技術やホトレ
ジスト技術により必要に応じてバターニングを行なって
ＶＳＳプレート３とする。
第１図に示すように、基板ｌの片面にほとんどの導体配
線パターン２が形成されているので、従来のごとき表裏
面の導体配線パターンを導通するスルーホール導体を必
要とし、ないが、必要に応じてスルーホール導体を形成
してもよい。また、第１図に示すように、基板１内部（
内層）にはＶ８８プレートはなく、基板ｌの裏面にＶＳ
Ｓプレート３が設けられている。
当該基板１０表面の導体配線パターン２上には、半導体
部品４や抵抗やコンデンサー５などの個別部品が搭載で
きる。
従来の裏面側導体配線が、当該個別部品４．５の下部に
位置するよ５にすると、例えば当該微細配線パターン２
が個別部品４により保護される。
なお第２図にて６は基板における端子部である。
本発明によれば、Ｖ８８プレートを有するプリント基板
において、従来は多層基板を用い、その内層にＶ８ｇプ
レートを設けていたのに対し、基板１を両面板とし、従
来裏面に設けていた配線のほとんどをファインプロセス
により表面に移し、基板ｌの表面に大部分の導体配線パ
ターン２を有するようにし、そのためにスペースのあい
た裏面ＫＶ８８プレートを設けるようにした。
そのため、従来のごとく、薄い樹脂板上にＶＢ１１プレ
ートを形成したものを複数枚積層し、かつ、表裏面配線
を導通するスルーホールをあけ、該スルーホール内部に
導体をつげＶ８８プレート入りの多層基板を形成するの
ではないので、材料面および製法面ともに簡略化、簡素
化され、基板単価を低下させ、板厚管理も容易となり生
産歩留が向上し、プレス加工が容易になり生産コストが
低減し、かつ、スルーホールを大幅に減らすことができ
るので断線ポテンシャルが低減し、ｖ８！１プレート３
が裏面にあるので、基板１の裏面配線にキズがつき問題
となることを回避できるとともに、当該プレート３によ
りシールド効果を奏することができた。
以上本発明者によってなされた発明を実施例にもとづき
具体的に説明したが、本発明は上記実施例に限定される
ものではなく、その要旨を逸脱しない範囲で種々変更可
能であることはいうまでもない。
例えば、前記実施例ではプリント基板について例示した
が、セラミック基板などにも適用できる。
本発明の基板は、メモリモジュール用プリント基板や電
算機用ボードやその他面付実装用プリント基板などとし
て好適に使用できる。
〔発明の効果〕
本願において開示される発明のうち代表的なものによっ
て得られる効果を簡単に説明すれば、下記のとうりであ
る。
本発明によれば、コストの低減された、かつ、信頼性の
向上した基板を提供することができた。
【図面の簡単な説明】
第１図は本発明の実施例を示す要部断面図、第２図は本
発明の実施例を示す要部平面図である。 ｌ・・・基板、２・・・表面配線（導体配線パターン）
、２・・・表面配線（導体配線パターン）、３・・・Ｖ
８Ｓプレート（電源プレート）、４・・・半導体部品、
５・・・コンデンサー、６・・・端子部。 ｋ＋− 第　　１　　図 第　　２　　図

Claims (1)

  1. 【特許請求の範囲】 １、Ｖｓｓプレートを必要とする面実装型プリント基板
    において、回路パターンのほとんどを部品搭載面に形成
    し、その反対側の面の大部分を電源プレートにすること
    によって信頼性の向上、及びコストの低減を実現可能と
    するプリント基板。 ２、基板が、ガラスエポキシ銅張プリント配線基板であ
    る、特許請求の範囲第１項記載の両面配線基板。
JP62042677A 1987-02-27 1987-02-27 両面配線基板 Pending JPS63211692A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP62042677A JPS63211692A (ja) 1987-02-27 1987-02-27 両面配線基板
KR1019880001839A KR970003991B1 (ko) 1987-02-27 1988-02-23 양면 메모리보드 및 그것을 사용한 메모리 모듈
US07/397,352 US5095407A (en) 1987-02-27 1989-08-23 Double-sided memory board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62042677A JPS63211692A (ja) 1987-02-27 1987-02-27 両面配線基板

Publications (1)

Publication Number Publication Date
JPS63211692A true JPS63211692A (ja) 1988-09-02

Family

ID=12642661

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62042677A Pending JPS63211692A (ja) 1987-02-27 1987-02-27 両面配線基板

Country Status (3)

Country Link
US (1) US5095407A (ja)
JP (1) JPS63211692A (ja)
KR (1) KR970003991B1 (ja)

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DE19854271A1 (de) * 1998-11-25 2000-05-31 Ilfa Industrieelektronik Und L Leiterplatte
JP2001212631A (ja) * 2000-02-01 2001-08-07 Tokai Rika Co Ltd 回路素子接続方法
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US6815621B2 (en) * 2000-10-02 2004-11-09 Samsung Electronics Co., Ltd. Chip scale package, printed circuit board, and method of designing a printed circuit board
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JP2008288119A (ja) * 2007-05-21 2008-11-27 Denso Corp 高電圧機器モジュール
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Also Published As

Publication number Publication date
US5095407A (en) 1992-03-10
KR880010641A (ko) 1988-10-10
KR970003991B1 (ko) 1997-03-24

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