JPS63193400A - Electrically writable read-only memory - Google Patents

Abstract

PURPOSE:To reduce the number of elements by connecting the source sides of plural memory cells connected to the same data line in common and providing a piece of a switch, which is conductive only when either of the word lines of the memory cells of the object of the common connection between the spot of the common connection and an earth potential is selected. CONSTITUTION:Within a range that the conduction of the memory cell is permissible by a parasitic capacitance coupling between a drain and a floating gate, the respective four memory cells M1-M4 and M5-M8 on the same data line D1, are made into one group, and their source sides are connected in common. Here, a gate input X1 when either of the word lines W1-W4 is selected, and the gate X2 when some of the word lines W5-W8 is selected go to high level respectively, and make enhancement transistors C1, C2 into ON respectively, and at the other cases, they make them into OFF. Thus, the number of the transistors to be inserted between the source side of the memory cell and the earth potential, can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a read-only memory (hereinafter referred to as UV-EFROM) electrically writable by ultraviolet light.

[Conventional technology]

To write to a UV-EPROM cell, apply a high voltage to the control gate and train, select the memory cell to be programmed using the word line and data line, and use high-energy electrons (hot electrons) generated near the pinch-off region. This is done by injecting the energy into the floating gate by jumping over the energy barrier of the gate insulating film.

On the other hand, other unselected memory cells connected to the same data line as the memory cell selected for writing have their gate potential at the ground level and a high voltage applied to their drains, and have floating gates. The potential of the floating gate increases due to parasitic capacitive coupling between the drains.

From this result, if the drain voltage at which the memory cell becomes conductive when the gate potential is at ground level is VDF, and this VDF is lower than the train voltage required for writing to the memory cell, the voltage required for writing is Unselected memory cells conduct and leak before the voltage is applied to the line.

It is known that when the number of memory cells leaking in this way increases, a voltage higher than VDF cannot be applied to the data line due to the current supply capacity of the circuit that applies a high voltage to the data line, and writing becomes impossible. ing.

Such a phenomenon becomes more and more noticeable as the miniaturization of memory cells progresses and the channel length becomes shorter. Therefore, as shown in FIG. 2, in the conventional UV-EPROM, enhancement transistors CA1 to CA4 are connected between the sources of the memory cells MAI to MA4 and the ground potential.
There are some that insert .

For example, when writing to memory cell MA, other unselected cells MA2 to MA connected to the same data line DA
4 is the inserted enhancement transistor CA2
Since the gate of ~CA4 is connected to the word lines WA and ~WA4, it is kept in the off state, so that it is disconnected from the ground potential. As a result, even if the unselected cells become conductive due to the parasitic capacitive coupling described above, the data line D
The voltage necessary for writing can be applied without affecting the potential of Al.

[Problem that the invention seeks to solve]

In the conventional configuration described above, a transistor must be provided for each memory cell to disconnect it from the ground potential when it is not selected, which has the drawback of increasing the number of elements and increasing the chip size.

[Means for solving problems]

The UV-EFROM of the present invention connects the sources of multiple memory cells connected to the same data line to the drains and
The floating gates are commonly connected within a range that allows conduction of the memory cells due to parasitic capacitance coupling, and one of the word lines of the memory cells to be commonly connected is connected between this common connection side and the ground potential. It has a transistor that becomes conductive only when selected.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, in which the same data line D1
The upper four memory cells Ml to M, and M s T=
Each of M a is set as one set, and their source sides are commonly connected.

In the figure, W1 to W8 are word lines for memory cell groups 1 to M8, etc., and C1 and C2 are word lines for memory cell groups M1 to M4. M...
An N-channel enhancement transistor, X, inserted between the commonly connected sources of M8 and the ground potential.
X2 is an enhancement transistor c1. This is the gate input of C. Here, the gate input x1 is the word line W
When any one of word lines W5 to W4 is selected, and when one of word lines W5 to W8 is selected, the gate X2 becomes high level and the enhancement transistor C
1+ Turns on C2 and turns it off at other times.

Assuming that data line p1 and word line W are selected to write data into four memory cells, transistor C2 is turned on and the sources of memory cells M and M8 are brought to ground potential. At this time, the four unselected memory cells M6 and M8 have their gate potentials at the ground level and a high voltage applied to their drains, and the data line D1 and memory cells M1 to M6
．． M.

The potential of each floating gate increases due to the parasitic capacitive coupling between the floating gate and the floating gate.

However, the source side is the enhancement transistor C2.
Since the enhancement transistor C1 is off, the sources of the memory cells other than the memory cells M, , M6 and M8 connected to the data line D1 are disconnected from the ground potential, and the potential of the data line D1 is not connected to the potential of the data line D1. No effect at all.

Furthermore, even if the memory cells M5, M6, and M8 are rendered conductive due to the above-described coupling, the effect on the data line D1 is slight because only three memory cells are rendered conductive. As a result, accurate writing can be performed with almost no adverse effect on the high voltage applied to the data line for writing into the memory cell M.

In this way, by forming a set of four memory cells, in the case of a 1 megabit UV-EFROM in which, for example, 1024 memory cells are connected on the same data line, the connection between the source side of the memory cell and the ground potential is achieved. The number of transistors inserted into the circuit can be reduced from 1024 to 256.

〔Effect of the invention〕

By adopting the configuration described above, the present invention enables writing even when the floating gate potential rises due to coupling during writing and the UV-EPROM memory cell becomes conductive, and the number of elements can be reduced. This has the effect of reducing the chip size.

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows a conventional example. D,, DA, . . . data lines, Wl to W8. WA. ~WA4...word line, M! ~M B, M A
1~MA4...Memory cell, CI, C2, CAI
, CA2... enhancement transistor, X,
, X2... Gate input signal.

Claims (1)

[Claims] The source sides of multiple memory cells connected on the same data line are commonly connected within a range that allows conduction of the memory cells due to parasitic capacitance coupling between the drains and floating gates of the memory cells, and the common connection point is connected to the ground. 1. An electrically writable read-only memory, characterized in that one switch is provided between the potential and the switch that becomes conductive only when one of the word lines of the memory cells to be commonly connected is selected.