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JPS63187350U - - Google Patents

Info

Publication number
JPS63187350U
JPS63187350U JP1987077936U JP7793687U JPS63187350U JP S63187350 U JPS63187350 U JP S63187350U JP 1987077936 U JP1987077936 U JP 1987077936U JP 7793687 U JP7793687 U JP 7793687U JP S63187350 U JPS63187350 U JP S63187350U
Authority
JP
Japan
Prior art keywords
semiconductor substrate
shielded
outside
cap
lead
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1987077936U
Other languages
Japanese (ja)
Other versions
JPH0749807Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987077936U priority Critical patent/JPH0749807Y2/en
Publication of JPS63187350U publication Critical patent/JPS63187350U/ja
Application granted granted Critical
Publication of JPH0749807Y2 publication Critical patent/JPH0749807Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16195—Flat cap [not enclosing an internal cavity]

Landscapes

  • Solid State Image Pick-Up Elements (AREA)
  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本考案半導体装置の一つの実施例を示
す断面図、第２図は本考案半導体装置の別の実施
例を示す断面図、第３図及び第４図は背景技術を
説明するためのもので、第３図は光集積回路の断
面図、第４図は光集積回路をパツケージに実装し
た光集積回路装置の断面図である。 符号の説明、２……リード、４……半導体基板
、４ａ……電極パツド、９……キヤツプ。 FIG. 1 is a sectional view showing one embodiment of the semiconductor device of the present invention, FIG. 2 is a sectional view showing another embodiment of the semiconductor device of the present invention, and FIGS. 3 and 4 are for explaining the background art. 3 is a sectional view of an optical integrated circuit, and FIG. 4 is a sectional view of an optical integrated circuit device in which an optical integrated circuit is mounted in a package. Explanation of symbols: 2...Lead, 4...Semiconductor substrate, 4a...Electrode pad, 9...Cap.

Claims (1)

【実用新案登録請求の範囲】 半導体基板の電極パツドにリードの先端部が直
接固定され、 上記半導体基板の表面がキヤツプにより外部か
ら遮蔽され、 上記半導体基板の底面又はそれと接続された放
熱板が外部に露出せしめられてなる ことを特徴とする半導体装置。[Claim for Utility Model Registration] The tip of the lead is directly fixed to the electrode pad of the semiconductor substrate, the surface of the semiconductor substrate is shielded from the outside by a cap, and the bottom surface of the semiconductor substrate or the heat sink connected to it is shielded from the outside. A semiconductor device characterized by being exposed to.
JP1987077936U 1987-05-23 1987-05-23 Optical integrated circuit device Expired - Lifetime JPH0749807Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987077936U JPH0749807Y2 (en) 1987-05-23 1987-05-23 Optical integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987077936U JPH0749807Y2 (en) 1987-05-23 1987-05-23 Optical integrated circuit device

Publications (2)

Publication Number Publication Date
JPS63187350U true JPS63187350U (en) 1988-11-30
JPH0749807Y2 JPH0749807Y2 (en) 1995-11-13

Family

ID=30926414

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987077936U Expired - Lifetime JPH0749807Y2 (en) 1987-05-23 1987-05-23 Optical integrated circuit device

Country Status (1)

Country Link
JP (1) JPH0749807Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009111334A (en) * 2007-10-12 2009-05-21 Panasonic Corp Optical device, manufacturing method thereof, and semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4728448U (en) * 1971-04-14 1972-12-01

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4728448U (en) * 1971-04-14 1972-12-01

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009111334A (en) * 2007-10-12 2009-05-21 Panasonic Corp Optical device, manufacturing method thereof, and semiconductor device

Also Published As

Publication number Publication date
JPH0749807Y2 (en) 1995-11-13

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