JPS63180153A - Lineback control method for cache storage - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to lineback control of data output from cache storage to main memory in a cache storage type data processing system, and particularly relates to lineback data transfer control in a cache storage type data processing system. The present invention relates to a lineback control method suitable for data processing systems that require starting, suspending, and restarting.

[Conventional technology]

In general, medium-sized and large-sized data processing systems are equipped with high-speed cache memory that stores part of the data in main memory, and access the cache memory to obtain the desired data to speed up processing. ing.

Cache storage consists of multiple lines, each line's data is addressed at a main memory line address boundary, and each line is comprised of multiple transfer units. In the store-in method, data is written to cache memory, and when that line is to be replaced,
Ejects the data of the relevant line to the main memory. This is called a lineback.

Conventionally, in a data processing system using this type of cache storage method, a data stack is provided to accumulate the discharge data of a line from the cache storage to the main memory, and data transfer from the main storage to the cache storage (
line transfer). In addition,
Publicly known documents related to this include, for example, Japanese Patent Publication No. 59-
No. 36350 can be mentioned.

[Problem that the invention seeks to solve]

As a system becomes larger, the amount of hardware for the entire system inevitably increases, so it becomes necessary to share resources as much as possible. However, in the above conventional technology, no consideration is given to sharing resources between data transfer from main memory to cache memory (line transfer) and data transfer from cache memory to main memory (line back).
In order to perform line transfer and line back in parallel, it is necessary to separately prepare a data bus, error detection and correction circuit (FCC circuit), etc., which requires an increase in the number of interface cables between cache memory and main memory, and an FCC circuit. An increase in the amount of resources used was inevitable.

On the other hand, when attempting to share resources between line transfer and line back, parallel operation of line transfer and line back becomes impossible, resulting in a problem of degraded performance.

An object of the present invention is to reduce the amount of hardware used in a cache storage type data processing system by sharing resources between line transfer and line back without degrading performance.

[Means for solving problems]

The present invention provides a first stack means for holding a plurality of transfer units read from the cache memory on the cache memory side.
A second stack means for holding a plurality of transfer units transferred from the first stack means is provided on the main memory side, and controls the start, interruption, and restart of lineback data transfer from the cache memory side to the main memory. Control means shall be provided to

[For production]

The first stack means on the cache storage side holds a plurality of transfer units of lineback data read from the cache storage. The second stack means on the main memory side includes the first
A plurality of transfer units transferred from the stack means are held and written to the main memory.

The control means suspends the transfer after the transfer of any transfer unit of lineback data is being transferred from the first stack means to the second stack means and restarts the transfer from the next transfer unit. .

As a result, when common resources (for example, bidirectional bus, FCC circuit, etc.) are used for line transfer and line back, line back is interrupted at the time when line transfer starts, and the common resource is released for line transfer. Line transfers can be processed with top priority. If line back is started again after line transfer is completed, line back data between cache memory and main memory will not malfunction.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows an embodiment of the present invention, showing a data processing device, a main storage device, and an interface thereof.

The data processing device 100 has store-in cache storage 1. ECC circuit 2, lineback read data stack 3, bidirectional bus switching circuits 4 and 5. It includes a cache storage hit detection circuit 6, a control circuit A7, and the like. The main memory device 200 includes bidirectional bus switching circuits 8 and 9, and a main memory write data stack 1 that stacks transfer data from the lineback read data stack 3.
0, a main memory 11, a data stack 12 for stacking line transfer data read from the main memory 11, a control circuit 813, and the like.

A bidirectional bus 1, which is a common resource for line transfer and line back, is connected between the data processing device 1100 and the main memory bag [200].
Connected by 4.

When a data request is issued from the instruction processing device to the cache memory 1, the hit detection circuit 6 in the data processing device 100 detects whether or not desired data exists in the cache memory 1. This logic is well known, so it will be omitted here. If the desired data exists in cache memory 1, one block (assuming 128 bytes) containing the desired data is read from cache memory 1, and
It is sent to the instruction processing device through the CC circuit 2. If the desired data is not in the cache memory 1, the data processing device 1
00 issues a line transfer request to the main memory 200, and transfers one line (5 lines) containing desired data from the main memory 11.
When the block (12 bytes) is received and stored in the cache memory 1, one block (128 bytes) containing the desired data is sent to the instruction main memory through the ECC circuit 2.

Below, a case in which the desired data in response to a request from the instruction processing device is not in the cache memory 1 will be explained in detail.

When fetching a desired line from the main memory 11 to the cache memory 1, an entry to be replaced on the cache memory 1 is determined. In the store-in type cache memory 1, if the contents of the entry to be replaced differ from the contents of the main memory 11, it is necessary to discharge the contents of the entry to the main memory, that is, to perform a lineback, and the contents of the entry to be replaced are If the content is the same as the memory 11, there is no need for lineback.

When the hit detection circuit 6 determines that the desired data is not present in the cache memory 1, the data processing device 100
A line transfer request is sent to the main storage device 200 from the main storage device 200 . At this time, if lineback is unnecessary, the hit detection circuit 6 sends a lineback unnecessary signal to the control circuit A7 and the control circuit B13. The control circuit A7 turns off the bidirectional bus switching circuit 4 and turns on the bidirectional bus switching circuit 5 on the data processing device side, and the control circuit B13 turns off the bidirectional bus switching circuit 8 and turns on the bidirectional bus switching circuit 9 on the main storage device side. As a result, the bidirectional bus 14 switches to a data transfer mode from the main memory bag [20o to the data processing device 100, that is, a line permission mode. 1 line read from main memory 11 (51
The line transfer data (2 bytes) is stacked in each data stack 12 in transfer units (32 bytes), and is transferred to the data processing device side in 16 times through the 32-byte bidirectional bus 14, and is transferred to the data processing device side in 16 times through the 32-byte bidirectional bus 14. At the same time as being written into the memory 1, the desired data is transferred to the instruction processing device. This completes the line transfer process.

If the desired data is not on the cache memory 1 and requires lineback, the data processing device 100 sends a line transfer request to the main storage device 200, and then the hit detection circuit 6 sends a line transfer request to the control circuit A7 and the control circuit B
A lineback request signal is sent to 13. Upon receiving the lineback request signal, the control circuit A7 turns on the bidirectional bus switching circuit 4 on the data processing device side and turns off the bidirectional bus switching circuit 5. Similarly, the control circuit B13 turns on the bidirectional bus switching circuit 8 and turns off the bidirectional bus switching circuit 9 on the main storage side.

In parallel with this, the lineback data (512 bytes) on cache memory 1 is read out 16 times in units of 32 bytes, and after error checking and correction in ECC circuit 2, the lineback data (512 bytes) is read out in units of 32 bytes and transferred in units of (3
2 bytes) are stored in each stack 3. At this time, if the bidirectional bus 14 is in lineback permission mode from the data processing device 100 to the main storage device 200,
Transfer of lineback data from stack 3 to stack 10 is started for each transfer unit.

During line back data transfer, when line transfer data is read from main memory 11 and preparation for line transfer is completed, main memory device 200 sends a line transfer pre-advice signal to data processing device t100. Upon receiving the line transfer pre-advance signal, the control circuit A7 stops sending data from the stack 3, and also turns off the bidirectional bus switching circuit 4 on the data processing device side for line transfer.
Turn on. In parallel with the operation of the control circuit A7, the control circuit B13 turns the main memory side bidirectional bus switching circuit 8 into
Turn on FF and 9. This causes the bidirectional bus 14 to enter line transfer permission mode.

Line transfer data is transferred 16 times (512 bytes in total) from the stack 12 in 32-bus transfer units, and at the same time as being written into the cache memory 1, desired data is transferred to the instruction processing device.

When the line transfer is completed, the main storage device 200 sends a line transfer end signal to the data control device 100.

Upon receiving the line transfer end signal, the control circuit A7 turns on the bidirectional bus switching circuit 4 on the data processing device side and turns off the bidirectional bus switching circuit 5 on the data processing device side, and in parallel with this operation, the control circuit B13 turns on the bidirectional bus switching circuit 8 on the main storage device side. Turn ON, and turn 9 OFF. As a result, when the bidirectional bus 14 enters the lineback permission mode again, the interrupted lineback is restarted, all transfer units are stored in the stack 10 and then written to the main memory 11, and the lineback is resumed. Complete the missing cache behavior if there is one.

FIG. 2 shows a detailed block diagram of the peripheral circuits of the cache memory 1 and the main memory 11, as well as the control circuit A7 and the control circuit B13.

If a cache miss occurs and lineback is not required,
The hit detection circuit 6 sends out a line transfer request signal 15 and a line back unnecessary signal 17. In response to the line transfer request signal 15, the main memory activation circuit 28 sends out a main memory activation signal 42 to activate data reading from the main memory 11. Also.

Due to the lineback unnecessary signal 17, the flip-flop 2
2.26 reset, flip flops 23 and 27
is set, the bus switching circuits 5 and 9 are turned on.
, the bus switching circuits 4 and 8 are turned off, and the bidirectional bus 14
is set to the data transfer mode from the main memory 11 to the cache memory 1.

When reading from the main memory 11 starts, the main memory activation circuit 2
8 sends out a set signal 43 for the read data registers 36, 37, and 38 (corresponding to the stack 12 in FIG. 1);
Read 512 bytes of data at once Data register 3
Set to 6,37.38. When the read data is set in the read registers 36, 37, and 38, a target selection signal is sent from the target selection circuit 29 to the selector circuit 4.
0, the target data is sequentially divided into 16 transfer units of 32 bytes, and transferred to the cache memory 1 via the bus switching circuit 9, the bidirectional bus 14, and the bus switching circuit 5.
Two bytes of data are sent.

When the line transfer is completed, the flip-flop 23°27
will be reset.

If a cache miss occurs and a lineback is required,
Line transfer request signal 15 as in case of line transfer only
is sent to the control circuit B13, and the main memory activation circuit 2
8 sends a main memory activation signal 42 to the main memory 11.

Simultaneously with this operation, the line back request signal 18 is sent to the control circuit A7, flip-flops 23 and 27 are reset, and flip-flops 22 and 26 are set, thereby turning on the bus switching circuits 4 and 8. The bus switching circuits 5 and 9 are turned off, and the bidirectional bus 14 is set to the data transfer mode from the cache memory 1 to the main memory 11. When the lineback data is read from the cache memory 1, the cache successive signal 16 is activated.
Counting circuit A19 and counting circuit B20 start counting operations to control 16 read data registers 30, 31, 32 (corresponding to stack 3 in FIG. 1) and selector 39. Since data is read from the cache memory 1 during line back in ascending order of intra-line addresses, the read data is stacked in order starting from the read data register 30 according to the count value of the counting circuit A19. In synchronization with this, the selector 39 sequentially selects data from the data register 30 according to the count value of the counting circuit B20. In this way, data read from the cache memory 1 is transferred to the bus switching circuit 4, bidirectional bus 14, and so on in 32-byte transfer units. 16 main memory write data registers 33, 34 that pass through the bus switching circuit 8 and are controlled by the counting circuit B20
．． 35 (corresponding to stack 10 in FIG. 1) and 33 onwards.

Writing to main memory 11 is performed by main memory write data register 3.
3, 34. Don't do this until all the data (512 bytes) is collected at 35.

When preparation for line transfer in the main memory 11 is completed during line back operation, the main memory activation circuit 28 sends out a line transfer pre-advance signal 24, the counting circuit B20 stops counting, and line back data transmission is temporarily interrupted. . At the same time, the flip-flops 22 and 26 are reset by the pre-advance signal 24, and the flip-flop 23 is reset.
and 27 are set, the bidirectional bus 14
is set to the line transfer mode from the main memory 11 to the cache memory 1, and line transfer is performed. Line transfer operation is similar to the case without lineback. The counting circuit A19 is in operation even while the line transfer data is being sent out, and the line back data from the cache memory 1 is continuously stacked in the read data registers 30, 31 and 32.

When the line transfer is completed, the main memory activation circuit 28 sends out a line transfer completion signal 25, and the flip-flop 23
and 27 are reset, flip-flops 22 and 2
6 is set, and when the bidirectional bus 14 is reset to the data transfer mode from the cache memory to the main memory 11, the counting circuit B20 is restarted and the cache read data registers 30, 31, 32 are reset. The remaining lineback data is then sent to the main memory 11.

In this way, when all the lineback data is in the main memory write data registers 33, 34, and 35, they are written to the main memory 11 all at once, and the lineback operation is completed.

The control circuit A7 serves as an external interface and receives a signal 44 for starting the counting circuit B20 and a signal 4 for interrupting counting.
5. It has a signal 46 for restarting counting and bidirectional bus switching signals 47 and 48, and can be arbitrarily controlled from the outside.

FIG. 3 shows the timing yardage when the present invention is applied when a lineback is required due to a cache miss. The data read out in 16 transfer units (32 bytes) from the cache memory 1 is stacked through the ECC circuit 2 after two cycles, and then linebacked through the bidirectional bus 14 which is in lineback permission mode. will be held.

When the transfer of the 13th lineback transfer unit is completed, preparation for line transfer is completed, bidirectional bus 14 is switched to line transfer permission mode, and line transfer from main memory 11 is performed. When the line transfer is completed, bidirectional bus 1
Switch 4 back to lineback permission mode and stack 3
The remaining three lineback transfer transfer units held in the main memory write stack 10 are transferred to the main memory write stack 10, and when all the data is collected, they are written to the main memory 11 to complete the line transfer process.

〔Effect of the invention〕

According to the present invention, by providing the function of starting, interrupting, and restarting lineback data transfer from cache memory to main memory, line transfer performance is not degraded.
Resources can be shared by lineback and line transfer, which has the effect of reducing the amount of hardware.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG. 2 is a block diagram of an embodiment of the present invention.
FIG. 3 is a detailed block diagram of the main parts in the figure, and a timing chart for explaining the present invention in detail. 1... Cache memory, 2... FCC circuit, 3
...Read data stack for lineback, 4.5,
8.9... Bidirectional bus switching circuit, 6... Hit detection circuit, 7... Control circuit A, 10... Data stack for main memory writing, 11... Main memory, 12... Main memory read data stack, 13...
Control circuit B, 14...bidirectional bus.

Claims (1)

[Claims] (1) In a data processing system equipped with a cache memory that stores multiple line data on the main memory,
A first stack means for holding a plurality of transfer unit data read from the cache memory for lineback on the cache storage side, and a plurality of transfer unit data transferred from the first stack means on the main memory side. A cache storage lineback characterized in that a second stack means is provided for controlling the data transfer from the first stack means to the second stack means, and a control means is provided for controlling the start, interruption, and restart of data transfer from the first stack means to the second stack means. control method.