JPH05233440A - Data transfer system equipped with buffer function - Google Patents

Abstract

(57) [Summary] [Purpose] In the data transfer method of a computer system that transfers data from a cache memory or main memory to a device, even if the data cannot be temporarily written to the device, calculation processing stops. To provide a data transfer method with a buffer function that does not exist. [Structure] If the data is present in the cache memory 2, the data is transferred from the cache memory 2 to the device 5, and if the data is not present in the cache memory 2, the data is transferred from the main memory 1. Device 5
Transfer to. When data cannot be written to the device 5 during data transfer to the device 5, the transferred data is temporarily held in the buffer 3 and
When the data becomes writable in the
Data is transferred to the device 5.

Description

Detailed Description of the Invention

[0001]

[Industrial application] In recent years, there has been a demand for higher speed computers. There is a distributed memory type computer as one of the methods for realizing the speedup of a computer. A characteristic of the distributed memory computer is that the number of processors can be increased. However, when the number of processors increases, the frequency of data transfer between processors increases, and conversely, data for one information exchange ( The amount of messages will be small (fine). Therefore, a technique for efficiently transferring a large number of small messages is required.

Further, in order to improve the performance of a single processor, a method of hierarchically configuring memories has been adopted in recent years. Even in a system having such a hierarchical memory, efficient message transfer is required. The present invention relates to a data transfer method in a computer system as described above, and more particularly to a data transfer method having a buffer function capable of efficiently transferring a large number of small messages.

[0003]

2. Description of the Related Art Conventionally, direct memory access (hereinafter referred to as DMA), software polling, interrupt processing, or the like has been used as a method for transmitting data to an output device. DMA is very effective for sending a large block of data, and efficient data transfer cannot be performed by software polling and interrupt processing.

However, in a parallel computer system having a large number of processors, the size of data transferred at one time tends to be very small. In this case, data transfer may be carried out by DMA or software may be used. It is not efficient to transfer data by polling or interrupt processing. In order to solve such a problem, a technique has been developed in which a message is transferred by the same operation as a flash operation for writing back the data registered in the cache memory to the main memory (JP-A-3-1506).
59).

The technology described in the above publication connects a processor, a cache memory, a main memory device, a port, a cache controller for controlling them, and a plurality of processor elements consisting of a common bus via the port. In the parallel computer system described above, the processor element is provided with a specific data transfer instruction, and the cache controller is provided with a mechanism for executing the specific data transfer instruction.

Then, the above-mentioned operation of writing the contents of the cache memory of the cache controller to the main memory device (a flush operation, that is, in the case of a cache miss, when data is registered from the main memory device to the cache memory, If data at another address already exists in the cache memory, and that data has been updated, the cache data is updated by a similar operation to the operation of writing the data already registered in the cache memory to the main memory. When the data exists in the memory, the contents of the cache memory can be directly transferred to the port via the common bus by the above specific instruction.

That is, a mechanism (hereinafter, this mechanism is referred to as a line send) for directly transferring a message from the cache memory to the device by an operation similar to that of flushing the contents of the cache memory to the main memory is provided. As a result, the timing of message transmission can be explicitly specified, and the overhead when activating message transfer is reduced.

In the above-mentioned conventional technique, however, when data cannot be written to the transfer destination device, the processing is stopped until the device becomes writable.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks of the prior art, and when transferring data to a device, if the data exists in the cache memory, In the data transfer method of the computer system, which transfers data from the cache memory to the device and transfers the data from the main memory to the device when there is no data in the cache memory, the data can be temporarily written to the device. It is an object of the present invention to provide a data transfer method having a buffer function, in which the calculation processing does not stop even when there is no status.

[0010]

FIG. 1 is a diagram showing the principle of the present invention. In order to solve the above problems, the present invention, as shown in FIG. 1, includes a processor 6, a cache memory 2 and a main memory.
The device 1 includes a memory 1 and a device 5, and a cache controller 4 that controls data transfer between them.
When the data is transferred to the cache memory 2, if the data exists in the cache memory 2, the data is transferred from the cache memory 2 to the device 5,
In the data transfer method of the computer system that transfers the data from the main memory 1 to the device 5 when there is no data above, the data transferred from the cache memory 2 and the main memory 1 to the device 5 is temporarily A buffer 3 for holding is provided.

When the data cannot be written to the device 5, the transferred data is temporarily held in the buffer 3 and when the data can be written to the device 5,
Data is immediately transferred from the buffer 3 to the device 5.
In addition to the above configuration, a memory with an ECC is used as the buffer 3, an end bit indicating the end of the data is written in the remainder bit of the ECC check bit, and the end bit is referred to It can be configured to confirm that the data has been transferred.

Further, a ring buffer can be provided on the main memory 1 as the buffer 3. Also,
Furthermore, at the time of task switch
By rewriting the value of the pointer holding the write address, the data to be sent can be instantly switched for each task.

[0013]

1 (b) is a diagram showing a data transfer image in the present invention. In the present invention, as shown in FIG. 1B, data exists in the cache memory 2,
If the device 5 has a free space, the data is transferred from the cache memory 2 to the device 5 (see FIG. 1 (b)), and the data exists in the cache memory 2. Cache if there is no space
Copy data from memory 2 to buffer 3 (Fig. 1
(See (b)).

When there is no data in the cache memory 2 and the device 5 has a free space, the data is transferred from the main memory 1 to the device 5 (see FIG. 1).
(Refer to (b)) If there is no data in the cache memory 2 and there is no free space in the device 5, the data is copied from the main memory 1 to the buffer 3 (FIG. 1 (b)). See).

When there is data in the buffer 3 and the device 5 has a free space, the device 5 is loaded from the buffer 3
The data is transferred to (see FIG. 1B).

[0016]

FIG. 2 is a diagram showing an embodiment of the present invention. In FIG. 2, 10 is a processor, 11 is a main memory, 12 is a cache memory, 13 is a ring buffer, 14 is a tag, and 15 is a tag. Is a device, 16 is a cache,
A controller, 17 is a comparator, 18 is a write pointer, 19 is a read pointer, 20 and 21 are multiplexers, 22 is a write buffer, 23 is a data bus, and 24 is an address bus.

In the figure, the processor 10, main
A data bus 23 is provided between the memory 11, the cache memory 12, the ring buffer 13, the device 15, and the write buffer 22, and data transfer to the device 15 is performed via the data bus 23. An address bus 24 is provided between the processor 10 and the main memory 11 and the tag 14, and reading / writing of data from / to the main memory 11 is performed by the address bus 2.
4 address signal.

The tag 14 holds the address of the data registered in the cache memory 12, and the main
Address bus 2 when reading data from memory 11
4 and the address held in the tag 14 are compared, and the address on the address bus 24 and the tag 14 are compared.
When the addresses held in the memory match, the data is read from the cache memory 12.

If the data to be read is not registered in the cache memory 12, (cache cache 12
In the case of a miss), the data is read from the main memory 11 and the read data is registered in the cache memory 12. Further, at that time, as described in the conventional example, when the data of another address already exists in the cache memory 12 and the data is updated, the data is written to the main memory 11. Then, the data read from the main memory 11 is registered in the cache memory 12.

The write pointer 18 and the read pointer 19 are pointers for instructing an address when writing data to the ring buffer 13 and an address when reading data from the ring buffer 13, and the comparator 17 writes data.・ Pointer 18 and read pointer 19
Value is compared and a pointer status signal pst indicating whether or not there is a free area in the ring buffer 13 is output to the cache controller 16.

The cache controller 16 is a line
Send instruction lsend, line send end instruction lsende
Cache status signal cst, device status signal dst, pointer status signal pst
Determines whether there is data in the cache memory 12 or the device 15 has an empty space, or whether the ring buffer 13 is empty.
Control signal cctl, memory control signal mct
The device control signal dctl is output to control the data transfer to the device 15.

The ring buffer 13 is the main memory 1
1 is used, and the read / write operation to the ring buffer 13 is performed by the multiplexer 21 by changing the address signal of the main memory 11 to the write pointer 18
And the read pointer 19 side is switched.
Therefore, from the main memory 11 to the ring buffer 1
In order to transfer data to the memory 3, first, the multiplexer 21 is switched to the address bus 24 side, and the main memory 1
The data is read from 1 and written in the write buffer 22, and then the multiplexer 21 is switched to the write pointer 18 side so that the data written in the write buffer 22 is designated by the ring pointer. This is done by writing to the address of the buffer 13.

FIG. 3 is a block diagram of the control mechanism in this embodiment. In FIG. 3, the same parts as those in FIG. 2 are designated by the same reference numerals. FIG. 4 is a diagram showing the first and second embodiments of the ring buffer 13 in the present invention. In the figure (a), 13a is a data field for storing data, and 13b is an end for storing an end bit indicating the end of a series of data (the end bit becomes 1 at the end of a series of data).・
The bit fields, and 18 and 19 are the write pointer and read pointer shown in FIG. 2, respectively.

When the data is read from the ring buffer 13, the data is read from the address designated by the read pointer 19, and when the data is written, the address designated by the write pointer 18 is read. Data is written to. In Figure 4 (a),
data0 and data1 are a series of data, and da
Since the last end bit of ta1 is 1,
It can be seen that data1 has been written to the ring buffer 13 up to the last data. Further, data2 is not the last data yet, and it is shown that the data is not written in the portion shown as empty in FIG. 4 (a).

FIG. 4 (b) shows a ring memory with ECC.
FIG. 13 is a diagram showing an example used as a buffer, 13a is a data field for storing data, and 13b is an end field for storing an end bit indicating the end of a series of data.
The bit field is shown, and the figure shows an example in which the memory is composed of five 8-bit modules module0 to module4.

As shown in FIG. 4B, in the case of a memory with an ECC, there is generally a bit left over. That is,
When 1-bit error correction and 2-bit error detection (SEC-DEC) are performed on 32-bit data, 7 check bits are required, and as shown in FIG.
1-bit unused bit appears in module4. In the embodiment shown in FIG. 4 (b), a ring buffer is constructed by using the unused bit of 1 bit as an end bit field.

Data transfer to the device 15 in the embodiment shown in FIG. 2 will be described below with reference to FIGS. Line send instruction is cache controller 1
6, the cache controller 16 determines whether the cache memory 12 has data, the device 15 has space, or the ring buffer 13 is empty.
Based on cst, the device status signal dst, and the pointer status signal pst, the following control is performed in each state. When there is data to be transferred to the device 15 in the cache memory 12 and there is a free space in the device 15 (transfer of data from the cache memory 12 to the device 15).

The cache controller 16 sets the cache control signal cctl to "read" and reads the data to be transferred to the device 15 from the cache memory 12. As a result, the data stored in the cache memory 12 is output to the data bus 23. The cache controller 16 also outputs a device control signal dctl to write the data read from the cache memory 12 into the device 15. When there is data to be transferred to the device 15 in the cache memory 12 and there is no free space in the device 15 (copying of data from the cache memory 12 to the ring buffer 13).

The cache controller 16 sets the cache control signal cctl to "read" to read the data to be transferred to the device 15 from the cache memory 12. As a result, the data stored in the cache memory 12 is output to the data bus 23. Further, the cache controller 16 switches the multiplexer 20 to the write pointer 18 side, and
The multiplexer 21 is switched so that the value of the write pointer 18 is given to the memory as an address.

Next, the cache controller 16 writes the memory control signal mctl to write the data on the data bus 23 read from the cache memory to the ring buffer. When there is no data to be transferred to the device 15 in the cache memory 12 and there is a free space in the device 15 (transfer of data from the main memory 11 to the device 15).

The cache controller 16 is a memory
The control signal mctl is set to “read”, and the data to be transferred to the device 15 is read from the main memory 11. As a result, the data stored in the main memory 11 is output to the data bus 23. Also, the cache controller 16 uses the device control signal dc
It outputs tl and writes the data read from the main memory 11 to the device 15. When there is no data to be transferred to the device 15 in the cache memory 12 and there is no free space in the device 15 (copying of data from the main memory 11 to the ring buffer 13).

The cache controller 16 is a memory
The control signal mctl is set to "read", the multiplexer 21 is switched to the address bus 24 side, and the data to be transferred to the device 15 is read from the main memory 11. As a result, the data stored in the main memory 11 is output to the data bus 23 and written in the write buffer 22.

Next, the cache controller 16 switches the multiplexor 20 to the write pointer 18 side, and the multiplexor 21 is provided so that the value of the write pointer 18 is given to the memory as an address.
Switch. Then, the cache controller 16
Writes the memory control signal mctl to write the data written in the write buffer 22 to the ring buffer 13.

At this time, the output of the comparator 17 for comparing the values of the write pointer 18 and the read pointer 19 is checked to prevent the overflow of the ring buffer 13. And the ring
When the overflow of the buffer 13 occurs, by failing the line send after that,
Prevent data loss. There is free space in device 15 and ring buffer 13
If there is data (transfer of data from the ring buffer 13 to the device 15).

The cache controller 16 is a multi
The plexers 20 and 21 are switched so that the value of the read pointer 19 is added to the memory, the memory control signal mctl is set to "read", and the data is read from the ring buffer 13. Then, the device control signal dctl is set to “write”, and the data is transferred from the ring buffer 13 to the device 15.

At this time, the read value of the end bit field ebf of the ring buffer 13 is checked, and if the data transfer is not completed, the data transfer to the device 15 is not completed. Tell the thing. As described above, according to this embodiment, when the ring buffer 13 is provided and the data is transferred from the cache memory 12 or the main memory 11 to the device 15, when the device 15 has no free space, Since the data to be transferred is stored in the ring buffer 13, the processing does not stop even if the data cannot be written to the device 15.

When executing a plurality of tasks,
Write pointer and read at task switch
By rewriting the value of the pointer according to the task,
Data read / write to the ring buffer can be switched instantaneously. Further, in the above embodiment, an example in which the ring buffer is provided on the main memory has been described, but the present invention is not limited to the above embodiment, and the buffer for holding the data transferred to the device is the main memory. It can be provided separately from the memory.

[0038]

As is clear from the above description,
In the present invention, when a buffer is provided and data is transferred from the cache memory or the memory to the device,
Since the data to be transferred is stored in the buffer when the device has no free space, the calculation process is not stopped even when the device cannot write the data.

Therefore, for example, in a processing system including a plurality of processors, even if the plurality of processors are not completely synchronized, or even if there is a variation in load, a delay in processing by a particular processor causes It is possible to perform efficient processing without stopping the processing of the processor.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention.

FIG. 2 is a diagram showing an example of the present invention.

FIG. 3 is a diagram showing a control mechanism in the embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a buffer in the present invention.

[Explanation of symbols]

 1, 11 Main memory 2, 12 Cache memory 3, 13 Ring buffer 4, 16 Cache controller 5, 15 Device 6, 10 Processor 7, 18 Write pointer 8, 19 Read pointer 14 Tag 17 Comparator 20 Multiplexer 21 Multiplexer 22 Write buffer 23 Data bus 24 Address bus

Claims (4)

[Claims] 1. A processor (6) and a cache memory
(2) and main memory (1) and device (5) and a cache controller that controls the data transfer between them
(4), when data is transferred to the device (5), if there is data in the cache memory (2), transfer the data from the cache memory (2) to the device (5), In the data transfer method of the computer system that transfers the data from the main memory (1) to the device (5) when there is no data in the cache memory (2), the cache memory (2) and the main memory ( A buffer (3) for temporarily holding the data transferred from (1) to the device (5) is provided, and when the data cannot be written to the device (5), the transferred data is temporarily stored in the buffer (3). A data transfer method with a buffer function characterized by holding and immediately transferring data to the device (5) from the buffer (3) when the data can be written to the device (5). 2. A memory with an ECC is used as the buffer (3), an end bit indicating the end of the data is written in the remainder bit of the check bit of the ECC, and a series of data is referred to by referring to the end bit. The data transfer system with a buffer function according to claim 1, wherein it is confirmed that the data has been transferred. 3. A main memory (1) as a buffer (3)
2. A data transfer system having a buffer function according to claim 1, further comprising a ring buffer provided above. 4. The data to be transmitted is instantly switched for each task by rewriting the value of the pointer (7, 8) holding the read / write address of the buffer (3) at the time of task switching. A data transfer method having the buffer function of item 1.