JPS63178544A - Manufacturing method of semiconductor device - Google Patents
Manufacturing method of semiconductor deviceInfo
- Publication number
- JPS63178544A JPS63178544A JP1158187A JP1158187A JPS63178544A JP S63178544 A JPS63178544 A JP S63178544A JP 1158187 A JP1158187 A JP 1158187A JP 1158187 A JP1158187 A JP 1158187A JP S63178544 A JPS63178544 A JP S63178544A
- Authority
- JP
- Japan
- Prior art keywords
- film
- fib
- semiconductor device
- metal film
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体装置の製造方法に関し、特にＦＩＢ
を用いた金属パターンの形成方法に関するものである。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
The present invention relates to a method of forming a metal pattern using the method.
従来よりＦＩＢ （集束イオンビーム）を用いた金属膜
形成方法は、ＦＩＢによる穴開け、切断等の加工技術が
可能なため、既成の半導体素子回路の変更や、回路上の
任意の点から電極パッドを採り出しての信号観察、また
転写に用いるマスク上のパターンの修正等に用いられて
いる。Conventional methods for forming metal films using FIB (focused ion beam) allow for processing techniques such as drilling and cutting using FIB, making it possible to modify existing semiconductor device circuits and create electrode pads from any point on the circuit. It is used to extract signals and observe signals, and to correct patterns on masks used for transfer.
第２図〜第４図にＦＩＢを用いた従来の金属膜形成方法
を示す。図において、１は素子の形成されたＳｔ（シリ
コン）基板、２はシリコン酸化物層、３はＡ１配線、４
はＦＩＢによる集束イオンビーム、５はパッシベーショ
ン膜、６はＦＩＢによるＷ（タングステン）デポジショ
ンを行うためのＷの化合物ガス、７はＦＩＢによるＷデ
ポジションで形成されたＷの層である。A conventional metal film forming method using FIB is shown in FIGS. 2 to 4. In the figure, 1 is an St (silicon) substrate on which an element is formed, 2 is a silicon oxide layer, 3 is an A1 wiring, and 4 is a silicon oxide layer.
5 is a focused ion beam by FIB, 5 is a passivation film, 6 is a W compound gas for performing W (tungsten) deposition by FIB, and 7 is a W layer formed by W (tungsten) deposition by FIB.
この従来の形成方法でＷ膜を形成するには、まず第２図
に示すように集束イオンビーム４でパッシベーション膜
５を開孔する。次に第３図のようにＷ化合物のガス６を
素子表面に流しつつ、任意のパターンで集束イオンビー
ムを照射すると照射領域のみにＷの膜７が形成される。To form a W film using this conventional forming method, first, as shown in FIG. 2, holes are opened in the passivation film 5 using a focused ion beam 4. Next, as shown in FIG. 3, when a focused ion beam is irradiated in an arbitrary pattern while flowing a W compound gas 6 over the element surface, a W film 7 is formed only in the irradiated area.
このＷ膜７を電極パッドとして利用することにより、Ａ
ｆｆｉ配線３の信号を観察することができる。また第４
図に示すようにＷｉ７を配線変更のための金属配線に用
い２つの、ｌ配線３間を配線接続することにより回路の
変更を行うことも可能である。By using this W film 7 as an electrode pad, A
The signal on the ffi wiring 3 can be observed. Also the fourth
As shown in the figure, it is also possible to change the circuit by using Wi7 as the metal wiring for changing the wiring and connecting the two l wirings 3.
しかるに以上のような方法では、Ｗの膜厚は集束イオン
ビームの総合電荷量に依存するため、広い面積で厚いＷ
の膜厚を得るためには長時間を要し、さらに大きな電荷
量を注入すると半導体装置上の能動素子の特性に悪影響
を与える恐れがある。However, in the above method, the W film thickness depends on the total charge amount of the focused ion beam, so a thick W film is formed over a wide area.
It takes a long time to obtain a film thickness of 1,000 yen, and injecting a larger amount of charge may adversely affect the characteristics of active elements on the semiconductor device.
また薄い膜の場合はＷの配線抵抗が高くなるうえに、開
孔部分側壁でのＷ膜のカバレンジが悪くなり、コンタク
ト抵抗が極めて高くなるという欠点があった。In addition, in the case of a thin film, the wiring resistance of W becomes high, and the coverage of the W film on the side wall of the opening becomes poor, resulting in an extremely high contact resistance.
本発明はこのような欠点を除去するためになされたもの
で、厚いＷの膜と開孔部での良好なカバレッジを得るこ
とのできる半導体装置の製造方法を提供することを目的
としている。The present invention has been made to eliminate such drawbacks, and an object of the present invention is to provide a method for manufacturing a semiconductor device that can obtain a thick W film and good coverage at the opening.
本発明に係る半導体装置の製造方法は、１つの金属膜の
形成をＦＩＢによる金属膜の形成と、選択ＣＶＤによる
金属膜の形成とにより行なうようにしたものである。A method for manufacturing a semiconductor device according to the present invention is such that one metal film is formed by forming a metal film by FIB and forming a metal film by selective CVD.
本発明においては、ＦＩＢで形成された金属膜上に、選
択ＣＶＤにより金属膜を堆積して１つの金属膜を形成す
るようにしたから、金属の膜を厚くでき開孔部でのカバ
レンジを良好なものにすることができる。In the present invention, the metal film is deposited by selective CVD on the metal film formed by FIB to form one metal film, so the metal film can be thickened and the coverage at the opening can be improved. can be made into something.
以下、本発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は本発明の一実施例による金属膜の形成方法を示
す。図において、８は選択ＣＶＤによって形成された、
電極バンドとして用いられるＷ層を示し、他の番号は従
来例の相当番号のものと同一あるいは相当物を示す。FIG. 1 shows a method of forming a metal film according to an embodiment of the present invention. In the figure, 8 was formed by selective CVD,
The W layer used as an electrode band is shown, and other numbers are the same as or equivalent to the corresponding numbers in the conventional example.
一般にＷの選択ＣＶＤは、デポジション領域が自動的に
選択され、Ｓｔや金属の上には膜が形成されるがシリコ
ン酸化膜等の上には膜が形成されないことが知られてい
る。しかもＣＶＤであるため、ＦＩＢの場合とは異なり
、荷電ビームを用いずに広い面積にわたって厚い膜を形
成することが可能である。It is generally known that in selective CVD of W, a deposition region is automatically selected, and a film is formed on St or metal, but not on a silicon oxide film or the like. Moreover, since it is CVD, unlike the case of FIB, it is possible to form a thick film over a wide area without using a charged beam.
本実施例方法によりＷ膜を形成するには、まず従来例の
第２図及び第３図に示したのと同じ方法で、ＦＩＢによ
りＷ＠を短時間で極めて薄く形成し、次に選択ＣＶＤに
よりＷ膜を上記ＦＩＢによるＷ膜よりも厚く形成する。In order to form a W film using the method of this embodiment, first, by the same method as shown in FIGS. 2 and 3 of the conventional example, W@ is formed extremely thinly in a short time by FIB, and then by selective CVD. The W film is formed thicker than the W film formed by the FIB.
このような本実施例によれば、１つのＷ膜の形成をＦＩ
ＢによるＷ膜形成と選択ＣＶＤによるＷ膜形成とにより
行なうようにしたので、開孔でのカバレッジのよい厚い
Ｗ膜を短時間で形成できる。According to this embodiment, the formation of one W film is performed by FI
Since the W film is formed using B and the W film is formed using selective CVD, a thick W film with good coverage at the openings can be formed in a short time.
またＦＩＢでの電荷の注入量も少なくでき、電荷による
素子特性への影響が軽減できるというメリットがある。Further, there is an advantage that the amount of charge injected into the FIB can be reduced, and the influence of charge on device characteristics can be reduced.
以上、上記実施例ではＷの場合を例にとって述べたが、
ＦＩＢで形成可能な金属であれば上記実施例と同様な効
果があることは言うまでもない・また半導体装置以外の
マスク等にも同様に使用可能である。The above embodiments have been described using the case of W as an example, but
It goes without saying that any metal that can be formed by FIB will have the same effect as the above embodiment, and can also be used for masks other than semiconductor devices.
なお、上記実施例では１つのＡＩ配線の上にＷ膜からな
る電極パッドを形成した場合を示したが、これは第４図
について説明したように２つのＡＩ！配線間の配線接続
の変更に用いて回路の変更に用いることもできる。In the above embodiment, an electrode pad made of a W film was formed on one AI wiring, but as explained with reference to FIG. It can also be used to change circuits by changing wiring connections between wires.
以上のように本発明に係る半導体装置の製造方法によれ
ば、１つの金属膜の形成をＦＩＢによる金属膜の形成と
選択ＣＶＤによる金属膜の形成とにより行なうようにし
たので、半導体素子の特性に悪影響を与えることなく厚
い金属膜を短時間で得ることができ、開孔部での良好な
カバレッジを得ることができ、コンタクト抵抗を下げる
ことができる効果がある。As described above, according to the method for manufacturing a semiconductor device according to the present invention, since one metal film is formed by forming a metal film by FIB and forming a metal film by selective CVD, the characteristics of the semiconductor element can be improved. It is possible to obtain a thick metal film in a short time without adversely affecting the surface of the metal, good coverage can be obtained at the opening, and the contact resistance can be reduced.
【図面の簡単な説明】
第１図は本発明の一実施例による半導体装置を示す図、
第２図、第３図、及び第４図は従来例を示す図である。
図において、１は素子の形成されたシリコン基板、２は
シリコン酸化物層、３はＡｌ配線、４はＦＩＢによる集
束イオンビーム、５はパッシベーション膜、６はＦＩＢ
によるＷデポジションでの供給源となるＷの化合物ガス
、７はＦＩＢによるＷデポジションで形成されたＷの層
、８は選択ＣＶＤで形成されたＷ層をそれぞれ示す。
なお図中同一符号は同−又は相当部分を示す。[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a diagram showing a semiconductor device according to an embodiment of the present invention;
FIG. 2, FIG. 3, and FIG. 4 are diagrams showing conventional examples. In the figure, 1 is a silicon substrate on which an element is formed, 2 is a silicon oxide layer, 3 is an Al wiring, 4 is a focused ion beam by FIB, 5 is a passivation film, and 6 is FIB
7 shows a W layer formed by FIB W deposition, and 8 shows a W layer formed by selective CVD. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (3)
よる金属膜の形成と、選択ＣＶＤによる金属膜の形成と
により行うことを特徴とする半導体装置の製造方法。(1) A method for manufacturing a semiconductor device, characterized in that one metal film is formed by forming a metal film by FIB (focused ion beam) and forming a metal film by selective CVD. Method.
特徴とする特許請求の範囲第１項記載の半導体装置の製
造方法。(2) The method for manufacturing a semiconductor device according to claim 1, wherein the metal film is a W (tungsten) film.
属膜に用いたことを特徴とする特許請求の範囲第１項又
は第２項記載の半導体装置の製造方法。(3) The method for manufacturing a semiconductor device according to claim 1 or 2, wherein the metal film is used as an electrode pad or a metal film for changing wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1158187A JPS63178544A (en) | 1987-01-20 | 1987-01-20 | Manufacturing method of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1158187A JPS63178544A (en) | 1987-01-20 | 1987-01-20 | Manufacturing method of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63178544A true JPS63178544A (en) | 1988-07-22 |
Family
ID=11781872
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1158187A Pending JPS63178544A (en) | 1987-01-20 | 1987-01-20 | Manufacturing method of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63178544A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0296331A (en) * | 1988-09-30 | 1990-04-09 | Texas Instr Japan Ltd | Semiconductor device and manufacture thereof |
| JP2003079473A (en) * | 2001-09-10 | 2003-03-18 | Delta Tooling Co Ltd | Cushion structure for seat |
| US6670717B2 (en) | 2001-10-15 | 2003-12-30 | International Business Machines Corporation | Structure and method for charge sensitive electrical devices |
-
1987
- 1987-01-20 JP JP1158187A patent/JPS63178544A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0296331A (en) * | 1988-09-30 | 1990-04-09 | Texas Instr Japan Ltd | Semiconductor device and manufacture thereof |
| JP2003079473A (en) * | 2001-09-10 | 2003-03-18 | Delta Tooling Co Ltd | Cushion structure for seat |
| US6670717B2 (en) | 2001-10-15 | 2003-12-30 | International Business Machines Corporation | Structure and method for charge sensitive electrical devices |
| US6858530B2 (en) | 2001-10-15 | 2005-02-22 | International Business Machines Corporation | Method for electrically characterizing charge sensitive semiconductor devices |
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