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JPS63173926U - - Google Patents

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Publication number
JPS63173926U
JPS63173926U JP1987068373U JP6837387U JPS63173926U JP S63173926 U JPS63173926 U JP S63173926U JP 1987068373 U JP1987068373 U JP 1987068373U JP 6837387 U JP6837387 U JP 6837387U JP S63173926 U JPS63173926 U JP S63173926U
Authority
JP
Japan
Prior art keywords
circuit
signal
parallel
photocoupler
resistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1987068373U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987068373U priority Critical patent/JPS63173926U/ja
Publication of JPS63173926U publication Critical patent/JPS63173926U/ja
Pending legal-status Critical Current

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  • Pulse Circuits (AREA)
  • Electronic Switches (AREA)
  • Logic Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案による信号入力回路の一実施例
を示す結線図、第2図は第1図の回路の動作を示
すタイムチヤート、第3図は本考案の異なる実施
例を示す結線図、第4図は従来の信号入力回路の
一例を示す結線図、第5図は第4図の回路の動作
を示すタイムチヤートである。 3:ホトカプラ、3b:ホトトランジスタ、1
5:放電抵抗、16:ダイオード、17:コンデ
ンサ、19:充電抵抗。
FIG. 1 is a wiring diagram showing one embodiment of a signal input circuit according to the present invention, FIG. 2 is a time chart showing the operation of the circuit of FIG. 1, and FIG. 3 is a wiring diagram showing a different embodiment of the present invention. FIG. 4 is a wiring diagram showing an example of a conventional signal input circuit, and FIG. 5 is a time chart showing the operation of the circuit shown in FIG. 3: Photocoupler, 3b: Phototransistor, 1
5: Discharge resistor, 16: Diode, 17: Capacitor, 19: Charging resistor.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 外部からの任意電圧または電流の入力信号をホ
トカプラを介して所定電圧の内部信号に変換する
信号入力回路において、ダイオードと抵抗との並
列回路にコンデンサを直列に接続した回路を前記
ホトカプラのホトトランジスタのコレクタ・エミ
ツタ通路に並列接続し、ダイオードと抵抗との並
列回路とコンデンサとの接続点を内部信号の出力
としたことを特徴とする信号入力回路。
In a signal input circuit that converts an arbitrary voltage or current input signal from the outside into an internal signal of a predetermined voltage via a photocoupler, a circuit in which a capacitor is connected in series to a parallel circuit of a diode and a resistor is connected to the phototransistor of the photocoupler. A signal input circuit connected in parallel to a collector-emitter path, and characterized in that the connection point between a parallel circuit of a diode and a resistor and a capacitor is used as an output for an internal signal.
JP1987068373U 1987-05-07 1987-05-07 Pending JPS63173926U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987068373U JPS63173926U (en) 1987-05-07 1987-05-07

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987068373U JPS63173926U (en) 1987-05-07 1987-05-07

Publications (1)

Publication Number Publication Date
JPS63173926U true JPS63173926U (en) 1988-11-11

Family

ID=30908129

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987068373U Pending JPS63173926U (en) 1987-05-07 1987-05-07

Country Status (1)

Country Link
JP (1) JPS63173926U (en)

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