JPS63164639A - Serial data transmission method - Google Patents

Abstract

PURPOSE:To receive a data and its high speed processing of a data in matching with a desired accuracy by making bit number of a data transferred from an AD converter to a processor variable. CONSTITUTION:A reception register 54 has a capacity accommodating the maximum bit number of AD conversion data and a reception bit number is set to a register 54a. A counter 54b counts the bit number of AD conversion data set serially. A coincidence detector 54c detects the coincidence of the content between the counter 54b and the register 54a. In sending a data serially, a processor sets a reception bit number to the register 54a to stop the data fetch to the reception register 54 by the output of the detector 54c produced when the data of the reception bit number enters the reception register 54 so as to allow the processor to fetch the data in the reception register 54. Thus, the bit number of the data sent serially from the AD converter to the processor is made variable.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for transmitting serial data between an analog-to-digital (AD) converter and a processor of an engine control system using an electronic control device.

[Conventional technology]

An engine control system using an electronic control device has a configuration as shown in FIG. In this figure, 10 is the engine cylinder, 12 is the piston, 14 is the throttle valve, 16 is the fuel injection valve, 18 is the spark plug, 20 is the intake valve, 22 is the exhaust valve, and 24 is the l5C (idle speed control).
The valve 26 is a starter. Various sensors are provided to control this engine. 28 is intake temperature, 30 is intake air amount, 32 is throttle opening, 34 is intake pipe pressure, 3
6 is a water temperature sensor, 38 is a crank angle, and 40 is an oxygen sensor. 42 is a processing unit that takes in the outputs of various sensors through an input interface 44, converts the analog input into digital data with an AD converter 46, processes it with a processor 48,
An ignition pulse (■), an injection control pulse (■), an ISO control pulse (■), etc. are output through the output ink face 52. 50
is a memory consisting of a ROM that stores processing programs for the processor 48 and a RAM that stores processing data and the like.

The AD converter 46 has the configuration shown in FIG.

This is a successive approximation type for each channel, a, b, ...
... is the analog input (sensor output) of each channel, C0MPa, b, ... is the comparator, M
PX is a multiplexer, SAR is a successive approximation register, D
AC is a digital analog converter, R1! G[I is DAC
LAT is a latch circuit that receives channel selection data C3D from the processor side.

Successive approximation type AD conversion is well known; initially, data is set in register SAH with the MSB being 1 and the rest being O.
In response to this, the DAC outputs Vcc/2, which becomes the reference voltage for the comparator COMP. latch to channel a
Given data to select , MPX is C0MPa
The output of
2), the next bit of MSB in SAR will also be 1, and in response to this, the DAC will output 3 V cc/4, and if the output of C0MPa is still H, the next bit of SAR will also be 1.
In this manner, the digital value for the analog human input a is successively created in the register SAH. When AD conversion is completed up to the last bit, processor C
The contents of the SAR (AD conversion value of analog input) are serially transmitted to the processor 48 to the PU. Receive register 54
, the clock selector 56, the clock control circuit 58, the reception end detection circuit 60, and the signal lines 11 to 13 are circuits for this serial transmission.

The processor 48 outputs A at a constant period of, for example, 4 mS.
D-converted data is captured, and channel selection data C3D is output for each cycle to specify the channel and sensor to be captured. When this C3D receives a start signal from the processor through the signal line 11, it is taken into the launch LAT.
The MPX performs channel selection according to the C3D of the launch and SAR.

The DAC etc. starts AD conversion operation of the channel selected by MPX. A lock CLK required for this AD conversion is sent from the processor side through the signal line 13. Immediately after the AD conversion is completed, serial transmission of AD converted data is started through the signal line 12.

As shown in FIG. 6, the signal line 12 is always at H (high) level, and becomes L (low) level when serial transmission starts.

This first L level is the start bit, and after this, a predetermined number of bits, generally 8 bits, of AD conversion data are transmitted.
Continues at the H1L level corresponding to 1.0 (These H and L levels are synchronized with the falling edge of the clock CLK, and reading (taking into the reception register 54) is performed using the clock CLK.
It is held at the beginning of the day. The start bit is not taken into the register, and therefore the 8 bits of data are taken into the receiving register 54 in the form of shifting sequentially from the end as shown in the figure. 12 returns to H level and prepares for AD conversion in the next cycle.

[Problem that the invention seeks to solve]

The AD converter has a data resolution of 8 bits, 10 bits,
It is classified into 12 bits, etc. On the other hand, the register of the receiving section of the microcomputer (processor) of the engine control system is 8.
Bits are the mainstream. Therefore, the AD of the 8-bit AD converter
Conversion data only needs to be serially transmitted once, but AD conversion data from a 10-bit or 12-bit AD converter is first transmitted in 8 bits.
It is a two-stage operation in which a bit is transmitted, and after confirming that it has been received, the remaining 2 or 4 bits are transmitted. This complicates control and increases the time required.

The present invention improves this point and changes the number of bits of serial transmission data according to the required resolution of the selected channel, so that even 10-bit or 12-bit AD converted data can be serially transmitted at one time. The aim is to shorten data transmission time, expand versatility, and prevent transmission errors.

[Means for solving problems]

The present invention provides a processor (48) of an engine control system.
and a multi-channel AD converter (46), a receiving register (54) having a capacity capable of accommodating the maximum number of bits of AD converted data, and a register (54a) in which the number of receiving bits is set. , a counter (54b) that counts the number of bits of serially transmitted AD converted data, and a coincidence detector (54c) between the contents of the counter and the contents of the register, are used to serially transmit AD converted data. , the processor sets the number of reception bits in the register, and the data is sent to the reception register by the output of the coincidence detector that occurs when the AD converted data serially transmitted from the AD converter enters the reception register by the number of reception bits. The feature is that the acquisition is stopped and the AD conversion data in the reception register is input to the processor.

[Effect]

According to this transmission method, it is possible to make variable the focus number of the converted data that is serially transferred from the AD converter to the processor, and to receive the AD converted data according to the desired accuracy (resolution) and to receive the data at high speed. This makes it possible to receive error-free variable bit data, making it extremely effective for use in engine control systems.

〔Example〕

FIG. 1 is an enlarged view of the serial transmission signal receiving section of FIG. 5, which is the main part of the present invention. In the present invention, the expected maximum number of serial transmission data is stored in this reception register 54, for example, 16.
It has a capacity of bits.

In this way, up to 16 bits of AD conversion data (resolution: 1/65536) can be transmitted in one serial transmission. Further, the number of bits of serial transmission data is made variable so that it is possible to specify how many bits are to be serially transmitted. In this way, channels a and c in Figure 5 will be AD converted with 8 bits, b and d with 10 bits, and the SAR, DAC, etc. will also be configured for a maximum of 16 bits), without errors (the end point will be certain). Serial transmission is possible (without any non-data being mixed in).

FIG. 2 shows the details of the receiving register 54. 54d is a register main body, to which control circuits 54a to 54c are attached. 54a is a register to which the number of received bits is sent from the processor, 54b is a counter that starts counting the clock CLK at the start bit (FIG. 6), and 54c is a coincidence detector (comparator). For example, if 10 bits are received, the processor CPU cents 10 to register 54a. In the AD converter 46, the A of the designated channel is
When the D conversion is completed and serial transmission of the contents of the register SAH begins, the signal line 12 is changed from H to L to output a start bit), and then data bits are serially transmitted.

When the counter 54b detects this start bit, it starts counting the clock CLK. Each serially transmitted data bit is sequentially shifted into the register 54d, and the state in which 10 bits are stored becomes as shown in the figure (the diagonal lines indicate register bits containing data). At this time, the detection circuit 54c finds a match between the content of the counter 54b and the content of the register 54a, and the detection circuit outputs a match signal S.

This signal S stops the receiving register 54d from taking in data (stops the shift clock), moves the data in the receiving register 54d to the data storage register 54e, and issues an interrupt request to the processor CPU. When the processor CPU receives this interrupt, it reads the contents of the data storage register 54e and stores it in the memory 50 (RAM).

Note that the clock control circuit 58 in FIG. 1 sends the clock CLK to the AD converter 46, the reception register 54, and the reception end detection circuit 60 (54c in FIG. 2), and the clock selector 56 selects this clock.

FIGS. 3 and 4 show flowcharts of the above processing procedure. Figure 3 shows the AD conversion unit, which performs initialization such as specifying the number of received bits, specifying clock timing (clock selection), clearing the data storage register 54e, and clearing the interrupt flag. (C3D issue), AD input bit number set (second
cent of the number of received bits explained in the figure), AD conversion is started (β1 is temporarily changed from H to L), and this is repeated. FIG. 4 shows interrupt processing. When the interrupt occurs, the conversion channel (C3D) is read, and the data read from the data storage register 5tte is saved in a register (RAM area) corresponding to the conversion channel.

The resolution increases as the number of bits of AD conversion data increases (8 bits gives a resolution of 1/256, 10 bits gives a resolution of 1/1024), but for engine control purposes, there are cases where such high resolution is not required, and cases where it is. There are various types.

It is pointless to perform multi-bit serial transmission even for items that do not require such high resolution, and there is also a waste of transmission time. In this respect, in the present invention, which channel can be specified with which resolution, and efficient data transmission becomes possible. Note that it is also possible to send the number of received bits to the AD converter, stop AD conversion at that number of bits, and immediately start serial transmission.

〔Effect of the invention〕

As explained above, according to the present invention, the number of bits of converted data serially transferred from the AD converter to the processor can be made variable, and AD converted data can be received in accordance with desired accuracy (resolution). faster receipt of
It becomes possible to receive error-free variable bit data, which is extremely effective for use in engine control systems.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the main parts of the present invention, Figure 2 is an explanatory diagram of the main parts of Figure 1, Figures 3 and 4 are flowcharts showing the processing procedure, and Figure 5 is A
FIG. 6 is a block diagram of the D converter and processor section, FIG. 6 is a time chart explaining serial data transmission, and FIG. 7 is an explanatory diagram of the engine control system. Figure 1 Figure 2 Shows the processing procedure Figure 3

Claims (1)

[Claims] A method for transmitting serial data between a processor (48) of an engine control system and a multi-channel AD converter (46), comprising: a receiving register (54) having a capacity that can accommodate the maximum number of bits of AD converted data. , a register (54a) for setting the number of received bits, a counter (54b) for counting the number of bits of serially transmitted AD conversion data, and a coincidence detector (54c) for matching the contents of the counter with the contents of the register. )
When serially transmitting AD converted data, the processor sets the number of received bits in the register, and this occurs when the serially transmitted AD converted data from the AD converter enters the receiving register for the number of received bits. A method for transmitting serial data, characterized in that the output of the coincidence detector causes data to be taken into the receiving register to be stopped, and the AD converted data in the receiving register to be taken into the processor.