SU1169173A1 - Device for translating serial code to parallel code - Google Patents

Abstract

A DEVICE FOR TRANSFORMING AN AFTER / JUVAL CODE TO PARALLEL, containing (n + 1) -discharge shift register, where n is the number of bits of the output code, clock generator, mode trigger, and element, with the first mode trigger input connected to the start input device messages, the output of the trigger mode is connected to the first input element-And, the second input of which is infor-. the device’s input and the output of the element I are connected to the input of the first digit of the shift register and the input of the clock pulse generator, the output of which is connected to the clock input of the shift register, which, in order to simplify the conversion while increasing the number of bits of the code being converted, Three generators of single pulses are entered into it, the elements NOT, OR, and the counter, and the shift register contains a group of additional bits, the input of the first of which is connected to the output of the (n + 1) -th bit of the shift register, and the output of the latter through serially connected first and second generators of single pulses - with a counting input of the counter, with inputs of zeroing the bit from the second to (n + -1) -th (where, 2, ..., n) shift register and through the element NOT (L with the first input of the OR element, the second with the input of which is connected to the first input of the mode trigger connected to the recording input of the set number of counter pulses, the output of the zero state indicator of which is connected via the third single pulse generator to the second trigger input of the СГ5 mode, and the output n the first- generator with single pulses coupled to gating inputs a q-ro of (n + q) -th bits of the shift register. oh

Description

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The invention relates to automation and computing and can be used in digital data transmission systems for converting serial code into parallel.

The purpose of the invention is to simplify when increasing the number of bits of information in the message to be converted.

The drawing shows a functional diagram of a device for converting a serial code into a parallel one.

The device contains the shift register 1, the trigger 2 mode, the element FROM the generator 4 clock pulses, the information input 5 of the device, the input 6 of the start of the device message, the element OR 7, the element NOT 8, the generators 9-11 of single pulses (GOI), the counter 12.

The mode trigger ensures that the device goes from a standby state to a functioning state and vice versa.

Element And provides the resolution of the output clock frequency from the GTI and the reception of a serial shift code

register.

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The shift register provides for the accumulation of the information to be converted into it in the form of a sequential code. Additional bits of the shift register (additional compared to the number of bits of the shift register of a known device) ensure that pauses, represented by a certain number of clock cycles, between the words of the converted code are taken into account.

GOI 9 provides the transfer of the converted code to the information receiver and allows the shift register to be transferred to the (initial) state, allowing the next progression cycle to begin.

GOI 10 provides for setting the shift register to the initial state and adding one to the counter, which completes the conversion cycle for the next word.

The counter ensures that the current number of words to be converted is memorized, and through GOI 11 it gives a pulse signal about the end of the conversion of the message.

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GTI provides information shift in the device shift register and information source.

Input code pulses prednaznach-. for receiving the information to be converted.

The OR element provides, on the first input, a record 1 for the first digit of the shift register, a signal that triggers the start of operation of the device, an incoming message start bus, a second input — a record 1 for the first discharge of the shift register and O for the rest of it, after reading each words of the converted information from the device.

The inverter is intended to match the pulse levels at the output of the GOI2 and at the second input of the OR element.

The device works as follows.

The input 6 of the beginning of the message receives a signal recording 1 in the first digit of the shift register 1 and in the counter 12 a number p equal to the number of n-bit words contained in one message of the serial code being converted. At the same time, this signal is fed to the input of trigger 2 of the mode, setting it to the position, which opens the IZ element, through which the code pulses go to the inputs of the shift register 1 and the 4 clock pulses generator from input 5. Shifts continue (n + q) cycles, i.e. until 1, recorded at the start signal of the message in the first bit of the shift register 1, progresses to (n + q + 1) -th bit. The signal from the output of the (n + q + 1) -ro bit goes to GOI 9, producing a pulse to read the first n-bit parallel code shift formed in bits from q-ro to the (n + + q) th register 1 shift the words of the message and for the triggering of the POINT. The latter produces a pulse that sets all bits, except the first, shift register 1 to position O, the first discharge of shift register 1 through the elements NOT 8, OR 7 to position 1 and arriving at the counter input of counter 12, after which the contents of counter 12 are reduced per unit.

Starting with the next (() -th clock cycle, the process of forming a parallel code from the next, containing in this message the n-bit word represented by the sequential code, repeats. This happens until the contents of the counter 12 after reading the sequential word in the message will not become zero. This signal of counter 12 will perceive GOI 11, will generate a pulse to bring the device into operation 73 4 the initial state: the trigger 2 of the mode will set the state prohibiting the passage of code pulses through the element 3, and the bits of the shift register 1 are set to position O. To convert and transfer the next message, it is necessary to re-impulse to the input 6 of the beginning of the message and write the number P to the counter 12.

Claims (1)

A DEVICE FOR CONVERTING A SERIAL CODE TO PARALLEL, containing (n + 1) -bit shift register, where η is the number of bits of the output code, clock, mode trigger, element And, and the first input of the mode trigger is connected to the input of the device message beginning, the output The mode trigger is connected to the first input of the AND element, the second input of which is the information input of the device, and the output of the AND element is connected to the input of the first bit of the shift register and to the input of the clock generator, the output of which is under It is connected to the clock input of the shift register, characterized in that, in order to simplify the conversion while increasing the number of bits of the converted code, three single pulse generators, NOT, OR, and counter elements are introduced into it, and the shift register contains a group of additional bits, the input of the first of which is connected to the output of the (n + 1) -th discharge of the shift register, and the output of the latter through the first and second single pulse generators connected in series - with the counting input of the counter, with the inputs of zeroing the discharge from the second o by the (n + d-1) -th (where q = 1,2, ..., η) shift register and through the element NOT with the first input of the OR element, the second input of which is connected to the first input of the mode trigger connected to the input recording the set number of counter pulses, the output of the zero state indicator is connected through the third single pulse generator to the second input of the mode trigger, and the output of the first single pulse generator is connected to the gating inputs from the qth to (n + q) -ft bits of the shift register. OTP