JPS63164229A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide many electrodes in the same chip size, by arranging two lines or a plurality of lines of the electrodes of the chip on each side of the chip, insulating and sealing tape carriers, arranging the tape carriers in two stages or a plurality of stages, and connecting the electrodes of the chip in two or more than two lines and external electrodes. CONSTITUTION:Electrodes 5 and 6 on a semiconductor chip 2 are arranged in two lines or more than two lines on each side of the chip 2. Conductor foils 9 and 11 are bonded to sheet shaped insulators 10 and 12 and a tape carrier 13 is formed as an intermediate electrode. The electrodes are insulated and sealed and stacked in two stage or in a plurality of stages. The chip electrodes 5 and 6 in two or more lines are connected to external electrodes 14. For example, a bump 7, which is provided on the inner electrode 5 on the chip, is made higher than a bump 8 by the thickness of the conductor foil 11 and an insulating foil 10 of the tape carrier 13. The bump 8 is connected to the conductor foil 9, and the bump 7 is connected to the conductor foil 11. The tape carrier 13 is divided into two parts before the external electrodes 14, and each conductor part is connected to each external electrode 14.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor devices, and in particular to the arrangement of electrodes on a chip of a large-scale integrated circuit (VLSI) with a large number of inputs and outputs, and the relationship between the chip electrodes and external electrodes. This is related to the electric bridge structure.

[Conventional technology]

As systems become larger and more highly integrated, the number of signals extracted from a chip and the number of signals input to a chip are increasing. As a result, TAB (Tap
e Automated Bonding) technology was born.

FIG. 3 shows the arrangement of electrodes on a conventional chip, and FIG. 4 shows the connection between the electrodes of the chip and external electrodes by the conventional TAB technique, and the conventional semiconductor device will be explained below using these diagrams.

First, as shown in FIG. 3, the electrodes on the chip are arranged in a line on each side of the chip, and this 4i structure is the same whether wire bonding technology is used or TAB technology is used.

Next, as shown in FIG. 4, a protruding electrode (hereinafter referred to as bump) (8) is formed on the electrode (6) on the chip, one of the leads of tape carrier Q3 is connected to the bump, and the other is connected to the external electrode. It is connected to.

[Problem that the invention seeks to solve]

Conventional semiconductor devices have a structure in which the electrodes of the chip are lined up in a row, as shown in Figure 3, so the number of electrodes is limited by the chip size, and as the number of inputs and outputs increases, the chip size cannot be increased. However, there was a problem in that the cost of each chip increased.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device that can have many electrodes with the same chip size.

[Means for solving problems]

In the semiconductor device according to the present invention, two or more rows of chip electrodes are arranged on each side of a thousand knobs, a tape carrier is insulated and sealed, and two or more rows of chip electrodes and external electrodes are separated by two or more rows. This is a connection between

[Effect]

In this invention, it has become possible to arrange the electrodes on the chip in two or more rows, which makes it possible to arrange more electrodes than the conventional limit on the same chip size, and the number of the same electrodes can be increased. If so, the chip size can be reduced.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows h'? of a semiconductor device according to an embodiment of the present invention. a, FIG. 1 fal is a sectional view, and 1st UjI+b+ is a plan view. As shown in Figure 1 (al), the hump (7) placed on the 'electrode (5) inside the chip is
A hump (
8), the m electric cylinder (9) of tape carrier 03 and the insulator cylinder are raised as high as the thickness of the θ value, and the bump (8)
is connected to the conductive foil (9), and the hump (7) is connected to the conductive foil at+.

In addition, the conductor 7 connected to the electrode (5) inside the chip
The convex at+ and the insulator cylinder ω are connected to the voltage V outside the chip.
iA (conductor foil (9) connected to 61 and insulator cylinder 0
It has a structure longer than ω. Next, as shown in FIG. 1 (bl), the tape carrier 01 is separated into two groups in front of the external electrode Q41, and each conductive portion is connected to the external electrode 041.

FIG. 2 shows the arrangement of electrodes on the chip (2), in which an electrode (5) on the inside of the chip and an electrode (6) on the outside are arranged in two rows on each side of the chip.

In the above embodiment, the present invention was applied to the connection between the chip electrodes and external electrodes when the chip electrodes were arranged in two rows, but when the chip electrodes were arranged in n rows (n = 2.3...) This invention can also be applied to.

Furthermore, the present invention can be applied not only when the electrodes of the chip are arranged parallel to each other but also when they are not parallel to each other.

Also, as shown in Figure 5, the bumps (7) on the inside of the chip
) and the thickness of the bumps (8) on the outside of the chip, and then attach the tape carrier to the bumps (8) and (7).
), the present invention can be applied even if the connection is made by bending between the two. In this case, the insulator 7fJaω of the tape carrier
Cutting the end face diagonally increases the strength of the tape carrier.

Further, as shown in FIG. 6, the same effect can be obtained by using a conductor wire to connect the tape carrier and the external electrode.

〔Effect of the invention〕

As described above, according to the present invention, the electrodes of the chip are
Since they are arranged in rows, more electrodes can be arranged on the same chip size, and if the number of electrodes is the same, the chip size can be made smaller.

[Brief explanation of the drawing]

1 and 2 show a semiconductor device according to an embodiment of the present invention, FIG. 1 fat is a sectional view showing the connection between the 1,000-knob electrode and the tape carrier, and FIG. 2 +bl is a sectional view showing the connection between the tape carrier and the external electrode. FIG. 2, which is a view from the top of the chip showing the connections, shows the arrangement of the electrodes on the chip. 3 and 4 show a conventional semiconductor device, FIG. 3 shows the arrangement of electrodes on a chip, and FIG. 4 is a cross-sectional view of the connection between a thousand-knob electrode and a tape carrier. 5 and 6 show semiconductor devices according to other embodiments of the present invention, FIG. 5 is a sectional view of another embodiment in which chip electrodes and external electrodes are connected, and FIG. 6 is a tape It is a figure of other examples which connect a carrier and an external electrode. ill is a die pad, (2) is a semiconductor chip, (3) is a passivation film, (4) is a resist, (5), (6)
) are electrodes, (7) and (8) are bumps, (9), at+ are conductive foils, 00), 0υ are insulator cylinders, α is tape carrier, circle is external electrode, OQ is conductive wire be. Figure 1 (1 1 type 1 pad 71g) (Pump Z
Fast guide netifugu? , //ii @ wood foil 3I and Lanbane 1 o odor 10.12 , 7 colors) East 1 moto morote resist U Qi 7' kiyatua 5, t @ o box (b) 74 ! ) 4p Electricity 41 luck d Figure 2 Figure 3 Figure 4 Figure 6 Figure 15゛Conductivity I book I table

Claims (1)

[Claims] The electrodes on a semiconductor chip (hereinafter referred to as a chip) have a structure in which two or more rows of electrodes are arranged on each side of the chip. A semiconductor device characterized in that a carrier (referred to as a carrier) is used as an intermediate electrode, and two or more rows of chip electrodes and external electrodes are connected by insulatingly sealing and stacking them in two or more stages.