JP2581532B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a semiconductor device having a plurality of semiconductor chips mounted on a mounting substrate.
The present invention relates to a semiconductor device mounted and modularized . 2. Description of the Related Art A semiconductor chip sealed in a package is
A semiconductor device having a high mounting density constituted by mounting a plurality of devices on a mounting substrate (module substrate) is published by Nikkei McGraw-Hill, Nikkei Electronics Supplement, no. 2 "Micro Devices" p150. The present inventor has found the following problems as a result of studying the above-mentioned semiconductor device. [0004] Since there is a limit in reducing the size of the package itself, it is difficult to increase the mounting density of semiconductor chips on a module substrate. An object of the present invention is to increase the mounting density of a semiconductor device. The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings. Means for Solving the Problems Of the inventions disclosed in the present application, typical ones will be briefly described as follows.
It is as follows. That is, a semiconductor device is constructed by connecting bump electrodes of a semiconductor chip to leads and connecting a plurality of semiconductor chips having the leads to wiring on a module substrate. According to the above-described means, since the semiconductor chip is not sealed with the package, the mounting density of the semiconductor chip on the module substrate can be increased. Hereinafter, embodiments of the present invention will be described with reference to the drawings.
explain. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS First, a technique which is a premise of the present invention will be described.
There is a technology for mounting the semiconductor device on a module substrate.
Will be described. (Mounting Technology 1) FIG. 1 is a plan view showing a mounting state of a module substrate of a semiconductor device.
FIG . 2 is a front view of the semiconductor device shown in FIG.
FIG. 2 is an enlarged side view showing the semiconductor device shown in FIG. 1 . In FIG. 1 to FIG. 3, reference numeral 1 denotes a module substrate formed by laminating a plurality of ceramic layers and wiring layers by a laminated ceramic, and eight semiconductor chips 4A, 4B and 8 semiconductors
Chips 4C and 4D are mounted. Semiconductor chip 4A,
4B, 4C, 4D, for example, which Sutatiku RAM is configured, not sealed by the package comprising a ceramic, resin, or the like, the semiconductor element and wiring shape
The formed surface is molded with silicone rubber 7 or resin 7. [0014] semiconductor chip 4A, 4B, 4C, each of 4D are bump electrodes 6 formed of solder or gold or the like is provided, rie de 5A to the bump electrodes 6, 5B, 5
C and 5D are TAB (Tape Automated Bondin)
g) connected by With respect to the surface, the semiconductor chip 4A is
Each lead 5A is laminated on the conductor chip 4B.
And the lead 5B have the same function.
Are connected by, for example, solder. For example, a lead 5A for inputting an address signal to the semiconductor chip 4A is connected to a lead 5B for inputting an address signal to the semiconductor chip 4B, and similarly, a lead for inputting and outputting data of the semiconductor chip 4A. 5A is connected to a lead 5B for inputting and outputting data of the semiconductor chip 4B. The semiconductor chip 4B adjacent to the module substrate 1
Each lead 5B is connected to a wiring (see FIG.
(Not shown), the decoder 3 and the module substrate 1
Mode 2 is connected. On the other hand, those having different functions, for example,
Lead 5A ₁ for inputting a chip select signal to the semiconductor chip 4A is not connected to the lead 5B ₁ for inputting a chip select signal to the semiconductor chip 4B, it is connected to the leads 3A of the decoder 3. Also, lead 5
B ₁ is connected to a lead 3A different from the lead 3A to which the lead 5A ₁ is connected. 8 by decoder 3
Pieces of the semiconductor chip 4A, has a configuration for selecting one of the semiconductor chips 4A or 4B from the 4B. The same applies to the back surface, and the semiconductor chip
4D is stacked on the semiconductor chip 4C,
The lead 5D and the lead 5C have the same function.
Are connected to each other with solder or the like. For example, semiconductor chips
Lead 5D for inputting an address signal to the top 4D
Is for inputting an address signal to the semiconductor chip 4C.
The lead 5C is connected to the semiconductor chip 4D.
The lead 5D for inputting and outputting data is a semiconductor chip
Connected to lead 5C for input / output of 4C data
Have been. Semiconductor chip 4 adjacent to module substrate 1
C, each lead 5C is arranged in the module substrate 1.
Decoder 3 and module board by wires (not shown)
1 lead 2. On the other hand, those having different functions, for example ,
Lead 5D ₁ for inputting a chip select signal to the semiconductor chip. 4D, the connection Sarezu the lead 5C ₁ for inputting a chip select signal to the semiconductor chip 4C,
It is connected to the lead 3A of the decoder 3. The lead 5C _1, the lead 5D ₁ is connected to the leads 3A different leads 3A connected, selects one of the semiconductor chips 4D or 4C among eight semiconductor chips 4D, 4C by the decoder 3 It has a configuration . [0019] As mentioned above, it has not been sealed in the package
The semiconductor chips 4A, 4B, 4C, 4D are
B to lead 5A, 5B, 5C, 5D
By mounting on the module substrate 1 , the mounting area is reduced, and many semiconductor chips 4A, 4B, 4
C, 4D can be mounted. That is, the mounting density of the semiconductor device can be increased. The semiconductor chips 4A, 4B and the semiconductor
By stacking the chips 4C and 4D, respectively,
Module substrate 1 with more semiconductor chips 4
A, 4B, 4C, and 4D can be mounted. Next, a modified example of the above-described mounting state will be described. FIG. 4 shows a partially mounted state of this modification.
It is a perspective view showing. In this modification, in addition to the above configuration,
A semiconductor chip 4E is further mounted on the body chip 4A.
I have . 5E is the lead of the semiconductor chip 4E, the same machine
Connected to the lead 5A having the function . On the other hand, those having different functions, for example,
Lead 5E ₁ for inputting a chip select signal to the semiconductor chip. 4E, instead of being connected to the lead 5A _1, 5B _1, and to different leads 3A leads 3A of the decoder 3 to read 5A _1, 5B ₁ is connected It is connected. Similarly, on the back surface of the module substrate 1, the semiconductor chip 4
Equipped with a further semiconductor chip on the D, and a three were laminated structure. (Mounting Technology 2) FIG. 5 is a side view showing another mounting state . In FIG. 5, 1A is the module board 1
A connection terminal of the surface, 1B is rear surface of the connection terminal.
In this mounting state, the semiconductor chip is placed on the surface of the module substrate 1.
The tops 4B, 4A, and 4E are stacked to form one set, and four sets are arranged. Similarly, the back surface of the semiconductor chip 4
C, 4D, and 4F are laminated to form one set, and four sets are arranged. In this mounting state, the semiconductor chips 4B, 4B
A, 4E, 4C, 4D, each of the main surfaces of 4F, Sunawa
Leads 5A, 5B, 5E, 5C, 5D, and 5F are connected.
By making the surface facing the module substrate 1
And the length of the leads 5A, 5B, 5E, 5C, 5D, 5F
Can be shortened . (Mounting Technology 3) FIG. 6 is a front view partially showing another mounting state, and FIG.
FIG. 7 is a side view of the mounted state shown in FIG. 6. In this mounting state, the semiconductor chip 4A mounted on the front surface of the module substrate 1 has its back surface facing the module substrate 1, and the semiconductor chip 4C mounted on the back surface of the module substrate 1 has its main surface mounted. The surface faces the module substrate 1 . Thus, both sides of the module substrate 1
When the semiconductor chips 4A and 4B are mounted,
4B lead 5B and semiconductor chip 4C lead 5C
And the same function will be faced.
Function lead 5B and lead 5C
Connected only by through wiring (through-hole wiring) 8
be able to. For example, a lead 5B for inputting an address signal to the semiconductor chip 4B is connected to a lead 5C for inputting an address signal to the semiconductor chip 4C by a through wiring 8. Similarly, the semiconductor chip 4B
The lead 5B, which is the data input / output terminal,
By being connected to the lead 5C is an input-output terminal of the data of the semiconductor chip 4C. On the other hand, those having different functions, for example ,
Lead 5B ₁ for inputting a chip select signal of the semiconductor chip 4B, different Deco by respective connection Sarezu individual wiring by penetrating wiring 8 is the lead 5C ₁ for inputting a chip select signal of the semiconductor chip 4C
Connected to the third order. That is, the lead 5B ₁ is connected to the decoder 3 provided on the surface of the module substrate 1, lead 5C ₁ is connected to the back surface of the decoder 3 of the module substrate 1
Have been. Here, the module substrate 1 in this mounted state has a single-layer structure made of a resin such as glass epoxy, for example, and has no wiring other than the through wiring 8 provided inside. Between the semiconductor chips 4B and 4C and the leads 2
Wiring or a decoder 3 (see FIGS. 6 and 7)
(Not shown) and the semiconductor chips 4B and 4C.
Subsequent wiring and the like are provided on the front and back surfaces of the module substrate 1 . Penetrating wiring 8 is the through hole formed by the module substrate 1, for example a drill or the like, in which form the shape of the deposition or electroless plating or the like, for example, a copper layer. As described above, the leads 5B and 5B having the same function
By connecting the C in penetrating wiring 8, a single layer structure has Na provided wiring other than the through wiring 8 on the module substrate 1
And the reliability of the module substrate 1 can be improved. Further, since the leads 5B and 5C having the same function are connected by the through wiring 8, the number of wirings provided on the front surface and the back surface of the module substrate 1 can be reduced. The module substrate 1 and the through wiring 8
May be formed of a laminated ceramic. In this case, wiring for connecting the semiconductor chips 4B and 4C to the leads 2 and wiring for connecting the semiconductor chips 4B and 4C to the decoder 3 are embedded in the module substrate 1. However, the number of these wires must be connected by through wires 8 .
Depending on what has different functions, such as module base
The semiconductor chip 4B on the surface of the plate 1 is connected to the lead 2 and the decoder 3
Connections since it is only providing the wires or the like, can be number of wires to be embedded is greatly reduced, increasing the reliability of the module substrate 1. (Embodiment) The present invention conceived based on the technology on which the present invention is based
The embodiment will be described below. FIG . 8 is used in the embodiment of the present invention.
FIG . 9 is a plan view showing two semiconductor chips, and FIG .
The state where the two semiconductor chips connected to the leads is
FIG. 10 is a longitudinal sectional view showing the apparatus from the direction II, and FIG.
It is a longitudinal cross-sectional view. In the semiconductor chip 4A used in the embodiment of the present invention, the arrangement of the bump electrodes 6A is arranged in order from the upper left corner.
Next, the bump electrodes 6A ₂ ... 6A _N−1 , 6A _N , 6A _{N + 1} .
_{N + M} is arranged, and bump electrode 6 is formed on semiconductor chip 4B.
B are sequentially arranged from the upper right corner to the bump electrodes 6B ₂ .
As to the arrangement of the _{N-1, 6B N ... 6B} N + 1, 6B N + M, bump power
The poles 6A and 6B are symmetrically arranged. Where the subscript is
The same thing that has become a bump electrode of the same function. With this arrangement, the main part of the semiconductor chip 4B is
When the surface and the main surface of the semiconductor chip 4A face each other,
Bump electrode 6B ₂ ... 6B conductor chip 4B _N-1, 6B _N ...
6B _{N + 1} and 6B _{N + M} are semiconductors having the same function.
6A ₂ ... 6A _N−1 , 6A _N , 6A
_{N + 1} ... 6A It will face _{N + M.} These symmetrically
The arranged bump electrodes 6A and 6B are respectively identical to each other.
Mode 5 is connected. On the other hand, those with different functions
For example, the bump electrodes 6A ₁ for inputting a chip select signal of the semiconductor chip 4A, the bump electrodes 6B ₁ for inputting a chip select signal of the semiconductor chip 4B is
By shifting the arrangement, they are connected to separate leads 5. [0041] 9 is an insulating material, to insulate the leads 5 bump electrodes 6A ₁ is connected insulated from the semiconductor chip 4B, also the leads 5 bump electrode 6B ₁ is connected from the semiconductor chip 4A . The leads 5 are formed into an appropriate shape after connecting the leads 5 with the semiconductor chips 4A and 4B facing each other. Then, a plurality of sets of the semiconductor chips 4A and 4B are arranged on the front surface and the back surface of the module substrate 1, respectively. As described above, by arranging the bump electrodes 6A and 6B symmetrically and connecting them to the same lead 5, the semiconductor chips 4A, 4B
The mounting density of B can be doubled. Hereinafter , all of the bump electrodes 6A and 6B are
The configuration in which the components are arranged to face each other is shown. FIG . 11 is a diagram showing a 2nd embodiment used in this embodiment.
FIG . 12 is a plan view showing one semiconductor chip, and FIG .
The state where the two semiconductor chips thus connected to the leads is
It is a longitudinal cross-sectional view shown from a direction. In this case, the semiconductor chips 4A, 4B
Different bump electrodes 6A ₁ and the bump electrode 6B ₁ and the pair of functions
At the main surface of the semiconductor chip 4B and the semiconductor chip.
When the main surface of the bump 4A faces, the bump electrode 6
A ₁ and 6B ₁ face each other. In this case, the van
Lead 5 flop electrode 6A ₁ is connected, the bump electrode 6
An insulating material 9 is provided between the lead 5 to which B ₁ is connected.
Each is isolated and insulated. Also, in the present embodiment,
As in the art, multiple sets were mounted in the longitudinal direction of the mounting board 1.
To use wiring that penetrates the mounting substrate 1
May be used. Although the present invention has been described in detail with reference to the embodiments, the present invention is not limited to the above-described embodiments, and may be variously modified without departing from the gist thereof. Needless to say. The effects obtained by typical aspects of the invention disclosed in the present application will be briefly described as follows. By connecting the semiconductor chips not sealed by the package to the leads by TAB and mounting the semiconductor chips on the module substrate, the mounting area is reduced, and many semiconductor chips can be mounted on the module substrate. Further, by laminating the semiconductor chips, more semiconductor chips can be mounted on the same size module substrate. Therefore, the mounting density of the semiconductor device can be increased.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing a state in which a semiconductor device is mounted on a module substrate . FIG. 2 is a front view of the semiconductor device shown in FIG . 1 ; FIG. 3 is an enlarged side view showing the semiconductor device shown in FIG . 1 ; FIG. 4 is a perspective view partially showing a mounted state of a modified example . FIG. 5 is a side view showing another mounting state . FIG. 6 is a front view partially showing another mounting state . FIG. 7 is a side view of the mounting state shown in FIG . 6 ; FIG. 8 shows two semiconductors used in the embodiment of the present invention.
It is a top view showing a chip . FIG. 9 shows the connection of the two semiconductor chips shown in FIG .
It is a longitudinal cross-sectional view which shows the continued state from the I direction . FIG. 10 shows two semiconductor chips shown in FIG . 8 as leads.
FIG. 2 is a longitudinal sectional view showing a connected state from a direction II . FIG. 11 shows two semiconductor chips used in this embodiment .
It is a top view which shows a top. FIG. 12 is a view for reading two semiconductor chips shown in FIG . 11;
FIG. 3 is a longitudinal sectional view showing a state of connection from a direction I. [Explanation of Signs] 1. Module board, 2, 3A, 5A, 5B, 5C, 5
D, 5E, 5F read, 3 decoder, 4A, 4B,
4C, 4D: semiconductor chip, 6A, 6B: bump electrode,
7: silicone rubber or resin; 8: through wiring; 9: insulating material.

Continuation of front page    (72) Inventor Masayuki Watanabe               3681 Hayano, Mobara-shi, Chiba Hitachi, Ltd.               Su Engineering Co., Ltd. (72) Inventor Toshio Kanno               1450 Josui Honcho, Kodaira City, Tokyo Stock Association               Inside the Musashi Plant of Hitachi, Ltd. (72) Inventor Seiichiro Tsukui               15 Asahidai, Moromachi, Iruma-gun, Saitama               Hitachi Eastern Semiconductor (72) Inventor Takashi Ono               64 Akita, Naganuma, Tennocho, Minamiakita-gun, Akita Prefecture               Electronics Co., Ltd. (72) Inventor Yoshiaki Wakashima               1450 Josui Honcho, Kodaira City, Tokyo Stock Association               Inside the Musashi Plant of Hitachi, Ltd.

Claims (1)

(57) [Claims] By symmetrically arranging the bump electrodes having the same function of the first semiconductor chip and the second semiconductor chip, the same function is provided in a state where the first semiconductor chip and the second semiconductor chip face each other. And the bump electrodes having different functions are connected to the same lead by facing each other. The arrangement of the bump electrodes having different functions between the first semiconductor chip and the second semiconductor chip is asymmetrical. While facing the semiconductor chip,
A semiconductor device comprising a set of semiconductor chips in which the bump electrodes having different functions are connected to different leads without facing each other. 2. By symmetrically arranging the bump electrodes having the same function of the first semiconductor chip and the second semiconductor chip, the same function is provided in a state where the first semiconductor chip and the second semiconductor chip face each other. And the bump electrodes having different functions are connected to the same lead by facing each other. The arrangement of the bump electrodes having different functions between the first semiconductor chip and the second semiconductor chip is asymmetrical. While facing the semiconductor chip,
A plurality of sets of semiconductor chips connected to different leads without facing the bump electrodes having the different functions are mounted on a mounting substrate, and one end of a flexible lead is connected to the bump electrode of the semiconductor chip. A semiconductor device wherein the other end of the lead is electrically connected to a wiring formed on the mounting substrate. 3. The set of semiconductor chips is mounted on both sides of one side and the other side of a mounting substrate, and among the leads, leads having the same function are conducted to a common wiring, and leads having different functions are made independent. 3. The semiconductor device according to claim 2 , wherein the semiconductor device is configured to be electrically connected to each corresponding wiring. 4. A first semiconductor chip and a second semiconductor chip, bump electrodes having different functions and insulators are symmetrically arranged;
2. The method according to claim 1, wherein the first semiconductor chip and the second semiconductor chip are opposed to each other, and the bump electrodes having different functions and the insulating material are opposed to each other .
4. The semiconductor device according to any one of items 3 to 3 .