JPS63163542A - Test circuit - Google Patents

Abstract

PURPOSE:To easily produce a test pattern by automatically reading out the change of an input signal from a storage circuit simultaneously with the occurrence of the read timing of the input signal. CONSTITUTION:A microcomputer test circuit which subjects the input signal supplied from the external to a prescribed processing based on program instructions and outputs the processing result to the external is provided with a storage circuit (shift register 110) where the change of a prescribed input signal is stored and a read control circuit (OR gate 109) which reads out the change of the input signal from the storage circuit 110 at the time of the occurrence of the input signal read timing by execution of program instructions. Consequently, the change of the prescribed input signal is stored in the storage circuit 110, and the read control circuit 109 automatically reads out the change of the input signal from the storage circuit 110 if the input signal read timing occurs in accordance with execution of program instructions. Thus, the test circuit whose actual operation is easily confirmed is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microcomputer with a built-in control program, and more particularly to a test circuit for a microcomputer.

[Prior Art] Conventionally, when a microcomputer with a built-in control program is installed in a predetermined device and operated in accordance with the control program, its operation (hereinafter referred to as actual operation) is known. In order to test the operation in advance, an input signal is supplied from the outside at each predetermined time as the control program progresses, and it is determined whether or not the planned actual operation is performed.

That is, the microcomputer shown in FIG.
The decoder 30 reads the program instruction 301 from the address 00.
2, and the decoder 302 supplies a control signal 303 to the control processing circuit 304 based on the program instruction 301.

The control processing circuit 304 executes predetermined operations based on the control signal 303 , generates new address information 305 , changes the storage contents of the rewritable storage device 307 , reads the same, and outputs data from the input terminal 320 via the AND circuit 309 . Generation of a control signal 308 for reading human input information and transfer of output information to an output terminal 330 were executed.

Therefore, in order to test the actual operation of the microcomputer, the microcomputer is connected to an integrated circuit tester and the microcomputer is caused to sequentially execute program instructions. During the execution of such program instructions, a group of input signals is supplied from the integrated circuit tester device to the input terminal 320 in synchronization with the timing at which the control processing circuit 304 outputs the control signal 308, and as a result, a group of output signals obtained at the output terminal 330. is compared with the expected value using an integrated circuit tester to determine whether the microcomputer is functioning normally. An example of a test pattern used in testing such a microcomputer is shown in FIG.

[Problems to be Solved by the Invention] However, in the microcomputer testing method using the above-mentioned integrated circuit tester device, the test pattern to be supplied to the microcomputer in advance is transmitted through the control signal 30.
8 occurs and input terminal 32.
0, and it takes a huge amount of effort to check the times at which the control signals are generated and to create a test pattern for actual operation.

An object of the present invention is to solve the above problems and provide a test circuit whose actual operation can be easily confirmed.

[Means for Solving the Problems] The present invention provides a test circuit for a microcomputer that executes predetermined processing based on program instructions on input signals supplied from the outside and outputs the processing results to the outside.
The test circuit includes a storage circuit that stores changes in a predetermined input signal, and a readout control circuit that reads changes in the input signal from the storage circuit when a timing to read the input signal occurs as a program instruction is executed. It is a feature.

[Operation] The test circuit according to the above configuration stores changes in a predetermined input signal in the storage circuit, and when the timing to read the input signal occurs as a program instruction is executed, the readout control circuit detects the input signal from the storage circuit. Automatically read out signal changes.

[Embodiment] FIG. 1 is a block diagram showing a first embodiment of the present invention,
In the figure, numbers 101 to 108 indicate structures corresponding to the structures 300 to 308 of the conventional example. 109 is an OR gate, 110 is a shift register, 111.112 is an AND gate, 113 is an OR gate, 114 is an inverter,
120 is a terminal to which an input signal is applied, 130 is an output terminal, and 140 is a test terminal to which a test signal is applied.

When a microcomputer is tested by an integrated circuit tester device, a logic value "0" is supplied to the test terminal 140, but when the microcomputer is incorporated into a predetermined device and used for actual use, a logic value "1" is supplied to the test terminal 140. is supplied.

During this actual use, the input read signal 108 has a logic value of "1".
”, the signal “1” from the input terminal 120 is sent to the control processing circuit 10 via the AND gate 111 and the OR gate 113.
4.

On the other hand, during the test when the logical value "0" is supplied to the test terminal 140, the output of the AND circuit 111 always becomes the logical value "0", but the output of the inverter 114 becomes the logical value rlJ, so the shift If the output of the register 110 (top pin) 110a is a logical value "1", the control signal 1
AND gate 11 when 08 transitions to logical value “1”
2 (or game) sends a logic value "1" to the control processing circuit 104 via 1'13. Since the shift register 110 is shifted at the falling edge of the OR circuit 109, the timing at which the test signal 140 changes from the logical value "1" to the logical value "0" and the timing at which the control signal 108 changes from the logical value "1" to the logical value "0" ” at the timing when the shift register 110 changes to
The memory contents of are shifted sequentially.

Therefore, as shown in FIG.
0, the logical value pattern is shifted to shift register 1.
The data is sequentially shifted and stored into 10 bits 110a to 110d.

Next, the control program is executed and the address information 105 is
changes to "address 01"..."address 80"...address rFO", and accordingly, the program instruction 101 read from the read-only memory 100 is executed, and for example, when the address is "address 80", the control signal is 108 is the logical value rOJ
When the logic value changes from 1 to 1, and then to 0 again, the most significant bit of shift register 110 is read out and supplied to control processing circuit 104 via AND gate 112 and OR gate 113. Similarly, when the rFO address is selected, the control signal 108 changes from the logic value "0" to the logic value "1".
, then when the logic value changes to “0” again, the bit is already 1.
Logic value being shifted from bit 10b to bit 110a
0'' is transferred from bit 110a to control processing circuit 104 via AND gate 112 and OR gate 113.

As explained above, in this embodiment, the logical value pattern stored in the shift register 110 is the control signal 1.
Since the signals are sequentially transferred to the control processing circuit 104 in response to changes in 08, there is no need to create a test pattern in advance by considering the timing at which the control signals will be output, making it possible to test the actual operation extremely easily. .

FIG. 5 is a block diagram showing the configuration of a second embodiment of the present invention. In this embodiment, the shift register 110 of the first embodiment
Instead, a read/write memory 410 is used. The falling edge of the test signal 540 is used for writing to the memory 410, and the rising edge of the read signal 508 is used for reading.

[Effects of the Invention] As explained above, in the present invention, changes in the input signal are automatically read out from the memory circuit as the input signal read timing occurs, so the time at which the read timing occurs is checked one by one. The effect is that test patterns for actual operation can be created without any trouble, and test pattern creation becomes extremely easy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of the first embodiment of the present invention, FIG. 2 is a timing chart showing the operation of the first embodiment, FIG. 3 is a block diagram showing the configuration of the conventional example, and FIG. 4 5 is a timing chart showing the operation of the conventional example, and FIG. 5 is a block diagram showing the configuration of the second embodiment of the present invention. 111.112.511.512 ......And gate, 113.513...Or gate, 114.51
4...Inverter, 109...
- OR gate (read control circuit), 110......shift register (memory circuit), 410......anytime read/write memory (read control circuit, memory circuit). Patent applicant Kiyoshi Kuwai, agent for NEC Corporation and patent attorney - Figure 3

Claims (1)

[Claims] A test circuit for a microcomputer that executes predetermined processing based on a program instruction on an input signal supplied from the outside and outputs the processing result to the outside, and the test circuit has a memory that stores changes in the predetermined input signal. 1. A test circuit comprising: a circuit; and a read control circuit that reads changes in the input signal from the storage circuit when a timing to read the input signal occurs as a program instruction is executed.