JPH07220499A - Pattern generator - Google Patents

Abstract

PURPOSE:To shorten the test time by generating a pattern within a test cycle after execution of block write function for example. CONSTITUTION:A selection circuit 3 selects the side of ALPG 1 and the pattern thereof is written, as a background pattern, into a device to be measured and an expectation memory 2. The ALPG 1 then generates a block write pattern in order to rewrite the content of the device to be measured. Subsequently, correct writing of the block write pattern into the device to be measured is verified. The content of a color register in the device to be measured is latched, at first, in a latch circuit 4. A mask data and a column selection signal at the time of block write are then inputted to a bit operation circuit 5 at address 0 thus determining a bit to be rewritten for every data bit of memory and a bit for holding the previous value. Output from the operating circuit 5 is inputted to a bit selection circuit 6 and the output from the latch circuit 4 is selected, along with the output from the expectation memory 2, for every bit and then they are verified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pattern generator for easily generating a test pattern when testing a memory IC having functions such as block write and flash write.

[0002]

2. Description of the Related Art The structure of a conventional pattern generator will be described with reference to FIG. In FIG. 2, 1 is an ALPG, 2 is an expected value memory, and 3 is a selection circuit. In the ALPG1, each signal of address, data and clock given to a device under test (not shown) is generated as a test pattern having regularity by calculation. On the other hand, expected value memory 2
Is a memory having the same bit width and address depth as the device under test. A specific pattern is written prior to the test of the device under test, and the address given from ALPG1 to the device under test at the time of test execution. It is a memory that receives a signal and outputs data according to the address. The selection circuit 3 sets the data output 1A from the ALPG 1 and the output 2A of the expected value memory 2 to ALPG
It is switched by the control output from 1.

Generally, random access memory (hereinafter R
In the AM) test, the expected value memory is not used, and the expected value is generated by the ALPG output to perform the test. However, RA with functions such as block light and flash light
In M, it is possible to individually control whether to rewrite the memory cell or retain the previous value for each data bit, and it is possible to rewrite the memory cells of a plurality of consecutive addresses in one cycle. It is difficult to generate data. Therefore, a data pattern after execution of block writing or the like is generated by a simulator program or the like and written in the expected value memory 2 in advance.

Here, the selection circuit 3 first selects the output of the ALPG1, and executes the cycle of the background pattern writing and the block write writing by the ALPG1. After that, the selection circuit 3 is switched to the expected value memory 2,
Perform a judgment test. As a result, it is possible to generate data that cannot be generated by the ALPG1 after executing the block write.

[0005]

In the conventional pattern generator, the pattern must be written in the expected value memory in advance before the test is performed. Therefore, when a plurality of tests are performed, the expected value is not satisfied for each test. There is a problem that the rewriting of the value memory is necessary and the test time becomes long. It is an object of the present invention to provide a pattern generation circuit that eliminates the time required to rewrite an expected value memory.

[0006]

To achieve this object, according to the present invention, an ALPG1 and an ALPG1 which generate a memory test pattern by a program and input the pattern to a device under test having a block write function or a flash write function. The input of the expected value memory 2 that inputs the same pattern as that input to the device under test, the output of ALPG1, the latch circuit 4 that latches the pattern, and the output of ALPG1, A bit operation circuit 5 that operates a bit for rewriting or holding device data, an output of the latch circuit 4, an output of the expected value memory 2, and a bit operation circuit 5.
Bit selection circuit 6 that selects the output from the output of
And a selection circuit 3 which receives the output of the ALPG 1 and the output of the bit selection circuit 6 and outputs a pattern to the device under test.
First, the selection circuit 3 selects the ALPG1 side, writes the ALPG1 pattern as a background pattern in the device under test, and also writes it in the expected value memory 2.
A block write or flash write pattern is generated from ALPG1, the contents of the device under test are rewritten, the contents of the color register of the device under test are latched in the latch circuit 4, and then the block write or flash is performed for each address. The mask data and the column selection signal at the time of writing are input to the bit operation circuit 5, the bit to be rewritten for each data bit of the memory and the bit holding the previous value are obtained, and the output of the bit operation circuit 5 is sent to the bit selection circuit 6. It is input, and the output of the latch circuit 4 and the output of the expected value memory 2 are selected for each bit, and it is verified whether the written block write pattern is correctly written in the device under test.

[0007]

Next, FIG. 3 shows the configuration of a memory having a block write function, which is a device under test. FIG. 3 is a functional block diagram of the memory, which includes memory cells 31 expanded in the X address direction, the Y address direction, and the bit direction, and uses the color register 32, the mask register 33, and the column selection register 34. The contents of color register 32 can be written to consecutive addresses in memory.

Next, the timing of the block write operation and the memory contents will be described with reference to FIGS. 4 and 7. For example, if the memory having the block write function is a DRAM, each function is determined by the level of the control signal (WB / WE, DFS) at the fall of the RAS / CAS clock of the external clock signal, and in general, the control The combination of signals and functions is as shown in FIG.

First, the load color register function of FIG.
That is, according to the timings shown in A to D of FIG.
The data written in E of A is the memory cell 3 of FIG.
1 as pattern data to be written in the color register 32
Set to. In FIG. 4A, D0 of the color register 32
Pattern data "0011" is stored in D3. FIG. 4A shows the state of the memory cell 31 viewed from the direction A in FIG. 3, in which data “0” is previously written as a background pattern in Y1 to Y4 of the Y address.

Next, the block write is executed at the timings A to D in FIG. First, WB / WE
Is fixed to “L”, and when DFS = “L”, the address X1 is input to the address terminal and D1 is input to the data terminal as shown in E and F of FIG. input.

Next, at the fall of CAS, DFS =
As shown by E and F in FIG. 4C, the address Y1 is input to the address terminal and the data terminal D2 is input. An address on the memory 31 that executes block write is selected by the addresses X1 and Y1.

In FIG. 4D, as an example, the block light is
Four consecutive addresses Y1 to Y4 are the targets of execution, and D1 stores the data "100" in the mask register 33.
1 ”is written, and the data“ 1110 ”is written in the column selection register 34 in D2. The address where the data is "1" represents the address where rewriting is permitted,
Of the data written in the mask register 33 and the data written in the column selection register 34, only the part where both registers are “1” is rewritten. In FIG. 4E, only the shaded portion is rewritten with the contents of the color register 32. As a result, after the block write is executed, it becomes as shown in FIG.

Next, the structure of the pattern generator according to the present invention for measuring the device of FIG. 3 will be described with reference to FIG. 1 in FIG. 1 is ALPG, 2 is an expected value memory,
3 is a selection circuit, 4 is a latch circuit, 5 is a bit operation circuit,
6 is a bit selection circuit.

In FIG. 1, the selection circuit 3 first selects the ALPG1 side, writes the pattern of ALPG1 as a background pattern in the device under test (not shown), and also writes it in the expected value memory 2.

Next, a block write pattern is generated from ALPG1, and the contents of the device under test (not shown) are rewritten. After that, in order to verify whether the block write pattern just written is correctly written in the device under test, first, the contents of the color register of the device under test shown in FIG. 3 are latched in the latch circuit 4.

Next, at address 0, the mask data at the time of block write and the column selection signal are input to the bit operation circuit 5, and the bit to be rewritten for each data bit of the memory and the bit holding the previous value are obtained. This arithmetic circuit output 5A
Is input to the bit selection circuit 6 and the output 4A of the latch circuit 4 is input.
And the output 2A of the expected value memory 2 are selected bit by bit.

[0017]

EXAMPLE Next, FIG. 5 shows the configuration of the example of FIG.
5, 41 to 43 are latch circuits, 15 is a data select circuit, 51 to 58 are gates, and 6A to 6D are selectors. That is, the latch circuit 4 of FIG. 1 is composed of the latch circuits 41 to 43 of FIG. 5, and the bit operation circuit 5 of FIG. 1 is composed of the data select circuit 15 and gates 51 to 58.
The bit selection circuit 6 in FIG. 1 is composed of selectors 6A to 6D.

The gates 51 to 54 of the bit operation circuit 5 are A
The outputs 11A to 11D of the LPG 1 are used as the first input on a one-to-one basis, and the output of the data select circuit 15 is used as the second input. The gates 55 to 58 use the outputs of the gates 51 to 54 one-to-one as the first input and the signal 5E as the second input.

Selectors 6A to 6D of the bit selection circuit 6
Are the bit operation circuits, with the outputs 14A to 14D of the latch circuit 41 of the latch circuit 4 receiving the outputs 11A to 11D of the ALPG1 as first inputs and the outputs 2A to 2D of the expected value memory 2 as second inputs. Gate 5 to 5
It is selected by the signal from 8 and output. The selection circuit 3 is A
The outputs 11A to 11D of the LPG 1 and the outputs 16A to 16D of the selectors 6A to 6D of the bit selection circuit 6 are input, and the signals 3A to 3D are output.

Next, the operation of the embodiment of pattern generation in the block write test according to the present invention will be described with reference to FIGS. 5, 6 and 8. Here, as an example, an example in which the data bit is 4 bits is shown.

First, the selection circuit 3 outputs the output 1A of the ALPG1.
Select ~ 1D and write the background pattern to the device under test. At this time, the same pattern is simultaneously written in the expected value memory 2. FIG. 6A shows an example of the state of the memory in which the background pattern is written. In FIG. 2, the X address is represented as AX and the Y address is represented as AY in the memory 31 of FIG. 3. When writing a background pattern, AX is first set to “0”, and AY is sequentially counted up from “0” to obtain the data. Data is written in bits as binary numbers such as 1, 2, 3, ..., And AX and AY are sequentially counted up to write a background pattern.

Next, data is set in the color register. In FIG. 8, DA is hexadecimal data “A”, that is, 2
The binary data “1010” is written in the color register 32 of the device under measurement and simultaneously set in the latch circuit 4.

Next, a block write process is executed.
In FIG. 8, the mask register 33 is set at the address “0” of AY.
The hexadecimal data “F” is set as DA and the data “1” is set as DB in the column selection register 34. In addition, the mask register 33 at the address “4” of AY
The hexadecimal data “E” is set as DA and the data “2” is set as DB in the column selection register 34. Similarly, at the address "8" of AY, the mask register 3
The hexadecimal data “D” is set as DA in 3 and the data “3” is set as DB in the column selection register 34.

When the block write process is executed in this state, the device under test has the pattern shown in FIG. That is, the portion surrounded by the thick line is rewritten by the block write to the hexadecimal data “A” set in the color register 32.

Next, in the read cycle, the output of the pattern generating circuit is treated not as write data but as expected value data. The selection circuit 3 of FIG. 5 is a bit selection circuit 6
Output 16A to 16D is selected, and ALPG1 has the same pattern as that at the time of executing the block write, that is, "F", D in DA.
"1" is output at B. “F” is input to the latch circuit 42,
“1” is latched by the latch circuit 43.

The output 15A of the data select circuit 15 is
The least significant bit of the hexadecimal data "1", that is, "1" is output by the control input signal 15B, and the bit operation circuit 5
Outputs 5A to 5D of hexadecimal data "F", and the bit selection circuit 6 selects outputs 14A to 14D of the latch circuit 41, which is a color register for all bits. As a result, the outputs 3A to 3D of the selection circuit 3 become "0101" like the outputs 14A to 14D of the latch circuit 41, and an expected value equal to the data of the Y address "0" of the device under test (not shown) is generated. .

In the cycle in which the Y address is "1 to 3",
Since the output 15A of the data select circuit 15 is "0",
The outputs 6A to 6D of the bit selection circuit 6 are the outputs 2A to 2D of the expected value memory 2, and the outputs 3A to 3 of the selection circuit 3 are output.
The output of the expected value memory 2 is output to D. The pattern of FIG. 6A is written in the expected value memory 2, and this matches the Y address “1 to 3” of FIG.

When the Y address is "4", the same pattern as written in the column selection register 34 at the time of block write, that is, the hexadecimal data "2" is written in the latch circuit 43, and the bit operation circuit 5 is masked for block write. The data, that is, the hexadecimal data "E" is output. The data select circuit 15 outputs the least significant bit 0 of the hexadecimal data “2”, so that the outputs 3A to 3 of the select circuit 3 are output.
The outputs 2A to 2D of the expected value memory 2 are selected as D. Therefore, the Y address "4" of the measured memory pattern 18 of the block write of FIG. 8 matches the address "4" of the pattern of the expected value memory 2 shown in FIG.

Next, when the Y address is "5", the data select circuit output 15A outputs the second bit "1" of the hexadecimal data "2", and the output 5A of the bit operation circuit 5
5D becomes "0111". As a result, the output 6A of the bit selection circuit 6 is selected as the output 2A of the expected value memory 2, and the bit "0" of the address "5" of the pattern of the expected value memory 2 of FIG. That is, "0" is output. As the outputs 6B to 6D of the bit selection circuit 6, the outputs 14B to 14D of the latch circuit 41 are selected and "101" is output.
As a result, the outputs 3A to 3D of the selection circuit 3 are "0101".
Thus, the pattern coincides with the pattern of the address “5” of the pattern after the block write in FIG. When the Y address is "8", the same process is performed and the pattern shown in FIG. 6A is obtained.

As described above, the ALPG generates the same test pattern as the block write cycle, and by switching the control signal, it is possible to generate the expected pattern after the block write.

Although the block write has been described in the embodiment of the present invention, the flash write function can also generate the expected value by fixing the data select circuit 15.

[0032]

According to the present invention, in the test of the memory device, the pattern after the execution by the block write function or the flash write function can be generated within the test cycle, and the data of the expected value memory can be obtained for each test. Test time can be shortened because there is no need to rewrite.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a pattern generation circuit according to the present invention.

FIG. 2 is a configuration diagram of a pattern generation circuit according to a conventional technique.

FIG. 3 is a time chart of block writing.

FIG. 4 is a configuration diagram of an embodiment according to the present invention.

5 is a configuration diagram of the embodiment in FIG. 1. FIG.

FIG. 6 is a state diagram of a memory in which data is written.

FIG. 7 is an explanatory diagram of a control relationship of a memory having a block write function.

FIG. 8 is an explanatory diagram showing an operation of an embodiment of pattern generation during a block write test.

[Explanation of symbols]

 1 ALPG 2 Expected value memory 3 Selection circuit 4 Latch circuit 5 bit arithmetic circuit 6 bit selection circuit

Claims (1)

[Claims] 1. An AL for generating a memory test pattern by a program and inputting the pattern to a device under test having a block write function or a flash write function.
PG1 and the expected value memory 2 which inputs the output of ALPG1 and inputs the same pattern as that input to the device under test, the latch circuit 4 which inputs the output of ALPG1 and which latches the pattern, and the output of ALPG1 A bit operation circuit 5 for calculating a bit for rewriting or holding data of the device under test, an output of the latch circuit 4, an output of the expected value memory 2 and an output of the bit operation circuit 5 are input, and one of them is selected. And a selection circuit 3 for inputting the output of ALPG1 and the output of the bit selection circuit 6 and outputting a pattern to the device under test. First, the selection circuit 3 selects the ALPG1 side, Write the pattern of ALPG1 to the measuring device as a background pattern, and also write it to the expected value memory 2.
A block write or flash write pattern is generated from PG1, the content of the device under test is rewritten, then the content of the color register of the device under test is latched in the latch circuit 4, and block write or flash write is performed for each address. The mask data and the column selection signal at the time are input to the bit operation circuit 5, the bit to be rewritten for each data bit of the memory and the bit holding the previous value are obtained, and the output of the bit operation circuit 5 is input to the bit selection circuit 6. Then, the output of the latch circuit 4 and the expected value memory 2
And the output of the above are selected for each bit to verify whether the written block write pattern is correctly written in the device under test.