JPS6316334U - - Google Patents
Info
- Publication number
- JPS6316334U JPS6316334U JP11046586U JP11046586U JPS6316334U JP S6316334 U JPS6316334 U JP S6316334U JP 11046586 U JP11046586 U JP 11046586U JP 11046586 U JP11046586 U JP 11046586U JP S6316334 U JPS6316334 U JP S6316334U
- Authority
- JP
- Japan
- Prior art keywords
- decoder
- input
- address
- bits
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015654 memory Effects 0.000 claims description 10
- 239000000872 buffer Substances 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 2
Description
第１図は本考案の一実施例のメモリアクセス回
路のブロツク図、第２図は従来のメモリアクセス
回路の概略を示すブロツク図である。
１〜４……メモリバンク、５〜１０……メモリ
データ入出力バツフア、１１……メモリバンク指
定デコーダ、１２……入出力バツフアデコーダ、
１３……データバス（上位８ｂｉｔ）、１４……
データバス（下位８ｂｉｔ）、１５……アドレス
バス（最下位２ｂｉｔを除く）、４０……アドレ
スバス、４１，４２……メモリ、４３，４４……
データバス（上位、下位８ｂｉｔ）。
FIG. 1 is a block diagram of a memory access circuit according to an embodiment of the present invention, and FIG. 2 is a block diagram schematically showing a conventional memory access circuit. 1 to 4...Memory bank, 5 to 10...Memory data input/output buffer, 11...Memory bank specification decoder, 12...Input/output buffer decoder,
13...Data bus (upper 8 bits), 14...
Data bus (lower 8 bits), 15... Address bus (excluding the lowest 2 bits), 40... Address bus, 41, 42... Memory, 43, 44...
Data bus (upper and lower 8 bits).
Claims (1)
１アドレス８ビツトデータでそのアドレスの最下
位２ビツトの組合わせによつてアドレス領域が４
つに分割されたメモリと、これらのメモリの各々
を選択するデコーダと、このデコーダの制御によ
り前記４分割されたメモリのデータを前記外部デ
ータバスから入出力する複数の入出力バツフアと
、これらの入出力バツフアを前記最下位２ビツト
の組合せにより前記アドレスの偶数もしくは奇数
に応じて前記上位もしくは下位８ビツトの外部デ
ータバスに対して前記４分割されたメモリのデー
タの入出力の制御を行なう制御用デコーダとから
構成されることを特徴とするメモリアクセス回路
。 Upper and lower 8-bit external data bus,
One address is 8-bit data, and the address area is 4 depending on the combination of the lowest 2 bits of that address.
a decoder that selects each of these memories; a plurality of input/output buffers that input and output data from the four-divided memory from the external data bus under the control of the decoder; Controlling the input/output buffer to control the input/output of the data of the four-divided memory to the external data bus of the upper or lower 8 bits according to the even or odd number of the address according to the combination of the lowest 2 bits. 1. A memory access circuit comprising a decoder and a decoder.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11046586U JPS6316334U (en) | 1986-07-17 | 1986-07-17 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11046586U JPS6316334U (en) | 1986-07-17 | 1986-07-17 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6316334U true JPS6316334U (en) | 1988-02-03 |
Family
ID=30989489
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11046586U Pending JPS6316334U (en) | 1986-07-17 | 1986-07-17 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6316334U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5320825A (en) * | 1976-08-11 | 1978-02-25 | Hitachi Ltd | Memory control system |
-
1986
- 1986-07-17 JP JP11046586U patent/JPS6316334U/ja active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5320825A (en) * | 1976-08-11 | 1978-02-25 | Hitachi Ltd | Memory control system |
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