JPS63158660A - Multiprocessor bus control system - Google Patents

Abstract

PURPOSE:To attain a communication even when a trouble is generated in one unit of a system bus by providing a bidirectional buffer connected in parallel to a shared RAM on the way of a system. CONSTITUTION:In an ordinary operation, unit groups connected to the system bus and unit groups connected to the system bus 2 independently and exclusively have the system bus to control. The delivery between the bus 1 and the bus 2 is carried out through the shared RAM3. However, for instance, when the trouble is generated in the CPU21, the contents of a RAM22 cannot be written in the RAM3 by the CPU21. In such a case, the CPU11 validates the bidirectional buffer 4 to make access directly to the RAM22, thereby, the communication can be maintained to the unit except the CPU21.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multiprocessor bus control system having a plurality of processors on a system bus used in a numerical control device, etc., and particularly to a multiprocessor bus control system that improves bus efficiency and The present invention relates to a multiprocessor bus control method that allows communication even when a failure occurs in some units.

[Conventional technology]

In numerical control devices, etc., the multiprocessor hash control method, in which a system is configured by connecting multiple processors, memories, etc. to one system bus, is widely used. Since multiple processors, memories, etc. are connected to the system bus, data in each memory can be shared, and communication between processors is also possible, so the system configuration is simple, highly versatile, and useful. .

[Problem that the invention seeks to solve]

However, this method shares one system bus, so when one processor is using the bus,
Another problem is that other processors cannot use the bus, which slows down processing time. One way to solve this problem is to connect the system buses via shared memory, but in this case, if a failure occurs in a unit connected to one system bus, communication between the system buses will be interrupted. The problem is that it becomes impossible to do so at all.

SUMMARY OF THE INVENTION An object of the present invention is to provide a multiprocessor bus control system that solves the above problems, improves bus efficiency, and allows communication even when one unit of the system bus fails.

[Means for solving problems]

In order to solve the above problems, the present invention provides a system bus (12) with a plurality of processors (11, 13,
, 21), a coexisting memory (3) placed in the middle of the bus, and a bidirectional buffer (3) connected in parallel to the shared memory (3).
4), and during normal control, communication is performed via the shared memory (3), and when a failure occurs in one of the processors (21), etc., the bidirectional buffer (4) ) is provided.

[Effect]

In normal operation, the unit group connected to the system bus (1) and the unit group connected to the system bus (2) can independently monopolize the system bus and perform control.

Communication between the system bus (1) and the system bus (2) takes place via a shared RAM (3).

However, if a failure occurs in the processor (21),
Since the contents of memory (22) cannot be written to shared RAM by processor (21), processor 1
By enabling the bidirectional buffer (4) and directly accessing the memory unit 1-(22), communication can be maintained for units other than the processor unit (21).

〔Example〕

An embodiment of the present invention will be described below based on the drawings.

FIG. 1 shows a block diagram of an embodiment of the present invention.

In the figure, 1 and 2 are the system hashs, and the shared RA
M3 and a bidirectional buffer 4 connected in parallel thereto.

The system bus 1 has a processor 11. ROM and RAM
A memory unit 12 including a RAM, a processor unit 13 including a RAM, and a display device (CRT) 14 are connected. Control can be executed by sharing the system bus 1 between these units.

The system has 2 has a processor unit 21 and RAM.
A memory unit 22 having a memory unit 22 and the like is connected thereto. The processor unit 21 and the memory unit 22 can exclusively use the system bus 2.

In this way, the units connected to system bus 1,
The units connected to the system bus 2 use the system bus independently and do not interfere with each other. Communication between both units is via shared RAM. That is,
The processor unit 11 writes the contents of the memory unit 12 to the shared RAM, and the processor unit 21 writes the contents of the memory unit 12 to the shared RAM.
Communication is performed by reading this data from the AM and writing it into the memory unit 22. Of course, communication in the opposite direction can also be performed by performing the opposite operation.

However, if a failure occurs in the processor unit 21, for example, even if the memory unit 22 is normal, the contents of the memory unit 22 can only be written to the shared RAM 3 by the processor unit 21, so the processor unit 11 The contents of unit 22 cannot be read. In this case, the processor unit 11 is connected to the processor unit 2 by means not shown.
1 is recognized, the bidirectional buffer 4 is enabled, and the contents of the memory unit 22 are read out via the bidirectional buffer 4. In some cases, the details of the failure of the processor unit 21 may be displayed on the display device (CRT) 14.

In this way, the efficiency of the system bus can be increased, and even if some of the units on one system bus fail, the units connected to system bus 1 and the other units connected to system bus 2 can be communication.

In the above example, the number of shared RAM and bidirectional buffer is one, but it is possible to use a plurality of them and expand the number of system buses accordingly.

Furthermore, enabling the bidirectional buffer 4 may be done by software or by hardware.

〔Effect of the invention〕

As explained above, in the present invention, a shared RAM and a bidirectional buffer connected in parallel to the shared RAM are provided in the middle of the system, which improves the efficiency of system bus usage and allows multi-channel multifunction that does not cause problems even in the event of a failure. A processor-based control scheme can be provided.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention.

Claims (1)

[Claims] (1) A multiprocessor bus control system in which a system bus has multiple processors has a shared memory placed in the middle of the bus and a bidirectional buffer connected in parallel to the shared memory, and is used for normal control. The multiprocessor bus is characterized in that communication is performed via the shared memory, and when a failure occurs in one of the processors, communication is performed via the bidirectional buffer. control method.