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JPS57162056A - Composite computer system - Google Patents

Composite computer system

Info

Publication number
JPS57162056A
JPS57162056A JP56047969A JP4796981A JPS57162056A JP S57162056 A JPS57162056 A JP S57162056A JP 56047969 A JP56047969 A JP 56047969A JP 4796981 A JP4796981 A JP 4796981A JP S57162056 A JPS57162056 A JP S57162056A
Authority
JP
Japan
Prior art keywords
common
computer
modules
memory device
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56047969A
Other languages
Japanese (ja)
Inventor
Yutaka Nakajima
Koji Shida
Yasushi Jinbo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Engineering Corp
Toshiba Corp
Original Assignee
Toshiba Engineering Corp
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Engineering Corp, Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Engineering Corp
Priority to JP56047969A priority Critical patent/JPS57162056A/en
Publication of JPS57162056A publication Critical patent/JPS57162056A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)

Abstract

PURPOSE:To reduce concurrence of a common memory, and to decrease occurrence of overhead, by using the common memory device in common by each computer system, and also using other computer in common to an individual main storage device of each computer. CONSTITUTION:A common memory device SM10 is used in common by plural computer systems 21a, 21b, and coupling modules 22a, 22b for connecting each system 21a, 21b to each other are provided and are connected by an interface signal line group 23. By these modules 22a, 22b, whether a memory address generated in a high rank computer system belonging to said modules 22a, 22b is an address to the system to be connected 21a or 21b, or not is detected. Subsequently, in accordance with a result of detection of the address, an access request is outputted to the other system 21b or 21a, and also when an access request approval has been sent back from the other system, individual main storage devices 15a, 15b are accessed under the control of CPUs 13a, 13b, and concurrence of the memory device SM is reduced.
JP56047969A 1981-03-31 1981-03-31 Composite computer system Pending JPS57162056A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56047969A JPS57162056A (en) 1981-03-31 1981-03-31 Composite computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56047969A JPS57162056A (en) 1981-03-31 1981-03-31 Composite computer system

Publications (1)

Publication Number Publication Date
JPS57162056A true JPS57162056A (en) 1982-10-05

Family

ID=12790142

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56047969A Pending JPS57162056A (en) 1981-03-31 1981-03-31 Composite computer system

Country Status (1)

Country Link
JP (1) JPS57162056A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61103258A (en) * 1984-10-24 1986-05-21 インターナショナル　ビジネス　マシーンズ　コーポレーション Dynamic allocation mechanism for memory system
JPS63158660A (en) * 1986-12-23 1988-07-01 Fanuc Ltd Multiprocessor bus control system
JPH03245959A (en) * 1990-11-27 1991-11-01 Kiriyama Seisakusho:Yugen Lapping method of glass instrument for physical and chemical experiment
JPH04112259A (en) * 1990-08-31 1992-04-14 Fujitsu Ltd Disaster recovery methods for multiprocessor systems
JPH09198355A (en) * 1997-03-07 1997-07-31 Hitachi Ltd Processor system
US5909052A (en) * 1986-03-12 1999-06-01 Hitachi, Ltd. Semiconductor device having plural chips with the sides of the chips in face-to-face contact with each other in the same crystal plane
US5968150A (en) * 1986-03-12 1999-10-19 Hitachi, Ltd. Processor element having a plurality of CPUs for use in a multiple processor system

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61103258A (en) * 1984-10-24 1986-05-21 インターナショナル　ビジネス　マシーンズ　コーポレーション Dynamic allocation mechanism for memory system
JPH0520776B2 (en) * 1984-10-24 1993-03-22 Intaanashonaru Bijinesu Mashiinzu Corp
US5909052A (en) * 1986-03-12 1999-06-01 Hitachi, Ltd. Semiconductor device having plural chips with the sides of the chips in face-to-face contact with each other in the same crystal plane
US5968150A (en) * 1986-03-12 1999-10-19 Hitachi, Ltd. Processor element having a plurality of CPUs for use in a multiple processor system
US6379998B1 (en) 1986-03-12 2002-04-30 Hitachi, Ltd. Semiconductor device and method for fabricating the same
JPS63158660A (en) * 1986-12-23 1988-07-01 Fanuc Ltd Multiprocessor bus control system
JPH04112259A (en) * 1990-08-31 1992-04-14 Fujitsu Ltd Disaster recovery methods for multiprocessor systems
JPH03245959A (en) * 1990-11-27 1991-11-01 Kiriyama Seisakusho:Yugen Lapping method of glass instrument for physical and chemical experiment
JPH09198355A (en) * 1997-03-07 1997-07-31 Hitachi Ltd Processor system

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