JPS63155720A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a shallow junction having preferable current/voltage characteristics by using a deeper amorphous layer than ion implantation depth for forming the junction to prevent a channeling at the time of ion implantation, thereby eliminating the influence of crystal defect upon ion implantation for forming an amorphous layer. CONSTITUTION:After a field oxide film 2 is formed on an N-type Si substrate 1, a gate oxide film 3 is formed. Then, a low resistance polycrystalline silicon is deposited to form a gate electrode 4. Thereafter, Si ions are implanted to form an amorphous layer 5 of 1000Angstrom thick in the substrate 1. Then, BF2 ions are implanted. Here, the B implanting depth is 900Angstrom , which is shallower than the layer 5. Thereafter, it is lampannealed to activate the B to diffuse the B, thereby forming a junction at a position deeper than the depth 1000Angstrom of a crystal defect 7 upon ion implantation for forming an amorphous layer to form a junction having preferable current/voltage characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention is directed to a good current
The present invention relates to a method for forming a shallow junction with voltage characteristics.

[Conventional technology]

Research into further miniaturization of LSIs is progressing toward higher performance and higher integration, but in order to realize miniaturized LSIs with gate lengths of approximately 0.5 μm or less, the junctions used as the source and drain of MO8FgT must be , the depth is 0.1
A shallow junction on the order of μm or less is essential. Conventionally, S
The method for forming a junction on a substrate is B when forming a P+N junction, and A when forming an N+P junction.
A method has been used in which ions of m or phosphorus are implanted and annealed in an electric furnace. However, it is difficult to form shallow junctions due to the diffusion of impurities during annealing. Therefore, instead of the conventional electric furnace annealing, lamp annealing, which can be activated without causing too much diffusion of impurities, is used as an effective method for forming shallow junctions.

[Problem that the invention seeks to solve]

When conventional low-energy ion implantation is performed, which is essential for forming shallow junctions as mentioned above, channeling occurs and impurities are implanted deeply, especially in the case of B, which has a small ion radius, even if the ions are implanted in a direction shifted from the low-index crystal axis direction. There is a problem that the bonding cannot be made shallow due to the intrusion. In order to suppress the above channeling, for example, before the ion implantation in step 8, ions that do not affect the electrical characteristics, such as St, are implanted.
A method has been proposed in which the vicinity of the surface of the Si substrate is made amorphous. According to this method, since ions are implanted into an amorphous layer, channeling can be prevented and shallow junctions can be formed. However, if the depth of the amorphous layer is increased to completely prevent channeling, However, due to the influence of crystal defects introduced by ion implantation for amorphousization, leakage current of the junction diode becomes large, and a shallow junction with good current-voltage characteristics cannot be formed.

[Means for solving problems]

The present invention solves the above-mentioned problems of conventional junction formation techniques and provides a method for forming a shallow junction of about 061 μm with good current-voltage characteristics. , a step of implanting inert first ions that do not affect the electrical characteristics of the semiconductor to form an amorphous layer on the semiconductor surface; and a step of forming an amorphous layer on the surface of the semiconductor, and A step of ion-implanting electrically active second ions to a shallower depth than that of the amorphous layer, and diffusing the impurity introduced by the second ion implantation through heat treatment, and increasing the depth of the impurity layer to the depth of the amorphous layer. It is characterized by including a process of making it deeper than it is.

[Effect]

Before explaining the present invention in detail, first, the experimental facts that led to the present invention will be described.

Si ions on St substrate with 150 keys, 2X 10
When ions are implanted under the conditions of cm, the cross section TEN shows that the amorphous state is formed from the surface to a depth of cL3μm.
This became clear from observation. Such a sample is subjected to electric furnace annealing at 900°C for 60 minutes or 950°C.
℃.

When lamp annealing is performed for 15 seconds, the amorphous layer and S
It was found that crystal defects occur at the interface of the t-crystal, that is, at a depth of 0.6 μm. As a result of investigating the relationship between the depth of crystal defects associated with ion implantation for amorphousization and junction leakage current, it was found that good junction characteristics are obtained when the junction depth is deeper than the crystal defects. It was found that the leakage current increases significantly when the junction depth is shallower than the crystal defect depth.

The present invention was made based on the above experimental facts, and in order to completely prevent channeling, the depth of the amorphous layer is 88.
By forming the bond to be deeper than the ion implantation depth, and then diffusing B through heat treatment, and making the junction surface slightly deeper than the depth of the crystal defect, a junction with good current-voltage characteristics is formed. It is something to do. That is, in the present invention, after forming an amorphous layer by first ion implantation,
In the step of implanting impurity ions by second ion implantation to form a junction, after implanting the second ions to a depth shallower than the depth of the amorphous layer formed by the first ion implantation, by heat treatment, The most important feature is that the impurity introduced by the second ion implantation is diffused to make the depth of the impurity layer slightly deeper than the depth of the amorphous layer. Examples will be described below based on the drawings.

〔Example〕

FIGS. 1(a) to +e) show an example in which the present invention is applied to MO8LSI manufacturing, and is a P-channel MO8LSI manufacturing example.
It shows the manufacturing process of SFET. In the figure, 1
is an N-type 81 substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a low resistance polycrystalline silicon gate electrode, 5 is an amorphous layer, 6 is a 21 layer (source, drain), 7 is an amorphous Crystal defects due to ion implantation for layer formation; 8 is an interlayer insulating film; 9 is A/, an electrode. First, as shown in FIG. 1(a), a field oxide film 2 with a thickness of 500X is formed on an N-type St substrate 1 according to the manufacturing process of a normal MO8LSI, and then a gate oxide film 6 with a thickness of 100X is formed. is formed in dry oxygen. Thereafter, low-resistance polycrystalline silicon to be used as a gate electrode is deposited to a thickness of 3000×, and a gate electrode 4 is formed using ordinary photolithography or electron beam phosphorography. Next, as shown in FIG. 1(b), prior to ion implantation to form P+N junctions used as sources and drains, Sl ions were implanted at 40ke.
Ion implantation is performed under the conditions of V, 2 X 10'''++s-2 to form an amorphous layer 5 in the N-type S1 group &1.When ion implantation is performed under the conditions shown here, the depth of the amorphous m5 is is 1000X. Next, as shown in Figure 1(c),
To form a P←N junction used as a source and drain, BF and ions were heated at 15 kaV and 2×1015c.
Ion implantation is performed under rn-2 conditions. Here, the reason for using BF ions is to obtain 8 low energy ions, and 15 keV BF rich ion implantation is! This is equivalent to 1.4 keV B ion implantation. Under the above BF and ion implantation conditions, the B implantation depth is 900K. After that, lamp annealing is performed at 950°C for 15 seconds to activate the B introduced by ion implantation, and at the same time, the first
As shown in Figure (d), B is diffused to form a bonding surface deeper than the depth 1oooX of crystal defects 7 caused by ion implantation for forming an amorphous layer. In this example, the depth of the P+N junction after annealing was 1100 mm. Moreover, since the crystallinity of the amorphous layer 5 is restored by this annealing and becomes a single crystal, the Sl ion implantation does not affect the electrical characteristics such as the resistance of the P layer 6.

After forming shallow P+N junctions for the source and drain using the method described above, the interlayer insulating film 8. AA electrode 9 is formed and a P-channel MO8FET is manufactured.

Figure 2 ta+, (b) shows P←N shown in this example.
The results show the concentration distribution of B in the junction in the depth direction measured by SIMS. Figure 2 (a) shows the case without heat treatment after ion implantation, and Figure 2 (b) shows the result after ion implantation at 950°C for 15 seconds. After lamp annealing. What is shown by a broken line in FIG. 2 ta+ is a measurement for comparison, in which only BF and ion implantation were performed without Si ion implantation. As shown in FIG. 2 (1), when the S1 ion implantation shown in this example is performed, the concentration distribution of B becomes a steep Gaussian distribution, and channeling is completely prevented. You can see that it is done. On the other hand, S1
As shown in the figure, without ion implantation, it is impossible to form a shallow junction with a distribution spread of about 430.1 μm due to channeling. In this way, by making the depth of the amorphous layer deeper than the implantation depth of 8,
A shallow P+N junction can be formed that completely prevents channeling. As shown in FIG. 2(b), the junction depth after lamp annealing (defined as the depth at which the B concentration becomes 1o"m-3) is 1100X. Next, the P+N
The reverse current-voltage characteristics of the junction are shown in FIG. As shown in the figure, the leakage current when -5V is applied is I x 1O-
A shallow junction with good current-voltage characteristics was obtained with a very small value of 9 A/aj). As mentioned above, B diffuses slightly during lamp annealing, so the junction depth is 1t.
ooX is slightly deeper than the depth of the amorphous layer, 1oooX. Therefore, in this example, the depth of crystal defects occurring at the interface between the amorphous layer and the crystal is shallower than the depth of the junction, so that good current-voltage characteristics as shown in FIG. 3 can be obtained. . For comparison, FIG. 4 shows the reverse current-voltage characteristics of a P+N junction formed by a method not according to the present invention.

This is when the depth of the amorphous layer is 30[]OX, but the depth of the junction is 1100X, which is a shallow junction. However, the depth of the crystal defects is smaller than the depth of the junction. Because it is deep,
As shown in FIG. 4, a large IJ current is shown. That is, by using the present invention, the value of the junction leakage current could be reduced to 171,000. As described above, according to the present invention, channeling can be completely prevented,
Moreover, shallow junctions with good current-voltage characteristics can be formed.

In the above explanation, Si was used as the ion species for ion implantation for amorphization, but Ge I
Any material, such as Ar, may be used as long as it does not ultimately affect the electrical characteristics. In addition, we have described the case of OF as the ion species for forming a junction, but of course, in the case of a P+N junction, other species such as B may be used, and in the case of an N+P junction, A@,
P etc. may be used.

Furthermore, although we have described the case where lamp annealing is used as the heat treatment, other annealing methods such as electric furnace annealing,
Needless to say, electron beam annealing, laser annealing, etc. may also be used.

〔Effect of the invention〕

As explained above, according to the present invention, since an amorphous layer is used that is deeper than the depth of ion implantation for forming a junction, channeling during ion implantation can be completely prevented, and the subsequent diffusion Since the effects of crystal defects associated with ion implantation to prevent amorphization are eliminated, there is an advantage that shallow junctions with good current-voltage characteristics can be formed.

Furthermore, since the ion implantation is into an amorphous layer, there is no need to perform the oblique ion implantation that is normally performed, and ion implantation can be performed from the vertical direction. Therefore, the present invention has great effects, such as eliminating the asymmetry of device characteristics that would be a problem in the case of oblique injection.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of the present invention, FIG. 2 is a diagram showing the measurement results of the concentration distribution in the depth direction of the junction formed according to the present invention, and FIG. FIG. 4 is a diagram showing the reverse current-voltage characteristics of a junction formed by a conventional method not according to the present invention. 1... N-type Si substrate 2... Field oxide film 6... Gate oxide film 4... Low resistance polycrystalline silicon gate electrode 5... Amorphous layer 6... p+m for source and train 7...Crystal defects accompanying ion implantation for forming an amorphous layer 8...Interlayer insulating film 9...At*extreme depth μm) The depth of B of the junction formed according to the present invention varies Diagram showing the measurement results of the concentration distribution at a depth of 2 μm)

Claims (1)

[Claims] A method for manufacturing a semiconductor device, comprising the steps of: implanting inert first ions that do not affect the electrical characteristics of the semiconductor to form an amorphous layer on the surface of the semiconductor; A step of ion-implanting electrically active second ions to a depth shallower than the depth of the amorphous layer formed by ion implantation, and diffusing the impurity introduced by the second ion implantation by heat treatment, and dispersing the impurity. A method of manufacturing a semiconductor device, comprising the step of making the depth of the layer deeper than the depth of the amorphous layer.