JPS63153645A - Parity generating circuit - Google Patents

Abstract

PURPOSE:To obtain a parity generating circuit with the simplified constitution by connecting n-stage [(n) is positive integer] of circuit units in series where a complementary data signal is inputted to a control electrode of each circuit means. CONSTITUTION:When a 1st data input signal is logic 1 (D0='1', inverse of D0='0'), circuit means 502, 503 are conductive and circuit means 504, 505 are nonconductive. Thus, a 1st input terminal information 1 is outputted to a 1st output terminal 512 and a 2nd input terminal information 0 is outputted to a 2nd output terminal 514. When the 1st data input signal is logic '0', the operation is reversed. That is, when the data input signal is logic '1', the input information is sent as it is and when the data input signal is logic '0', the information inversed is sent to the next stage. Thus, 4 stages of circuit units 501 are used to generate parity of data length 4-bit.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a parity generation circuit in an electronic circuit, particularly a semiconductor integrated circuit.

<Prior Art> A method of adding parity pits to a data bit string to improve the reliability of electronic circuit systems has been widely used.

Table 1 is a truth table of odd parity (Po) and even parity (Pe) for a data string of 4-bit data (Do, D,, D2.D,). Conventional examples of circuits that are added to bit data strings and generate these parity pits are shown in FIGS. 9 and 1O. That is, FIGS. 9 and 10 show N-channel MO5I
-A parity generation circuit using transistors. In the circuits of FIG. 9 and FIG. 1O, Di, Di (i=0 to
3) are mutually complementary data input signals; FIG. 9 shows an odd parity generation circuit (odd parity output PO), and FIG. 1O shows an even parity generation circuit (even parity output Pe).

In these circuits, the drive ability of the load transistor 101 or 201 needs to be set smaller than the drive ability of the drive transistor whose gate inputs the data input signal, so the parity output Pa or P
The problem is that the rising speed of e is slower than the falling speed.

A parity generation circuit with a CMO5 configuration that solves this problem and further reduces current consumption is shown in FIG. (i-0 to 3) are mutually complementary data input signals, and FIG. 11 shows an odd parity generation circuit,
The figure shows an even parity generation circuit.

<Problems to be Solved by the Invention> The parity generation circuit shown in FIGS. 11 and 12 above solves the problem that the rising speed of the parity output is slower than the falling speed, and further reduces current consumption. However, when this parity generation circuit is applied to an integrated circuit device, the wiring becomes complicated because mutually complementary data input signal lines are concentrated in the parity generation circuit, and the logic that determines the connection relationship of transistors becomes complicated. Due to the complicated configuration, logical division, that is, distributed arrangement on a layout pattern becomes difficult, resulting in a problem that the layout pattern of the parity generation circuit section becomes extremely complicated. This becomes more noticeable as the data length increases.

Means for Solving the Problems> The present invention has been made with the aim of solving the above-mentioned problems, and provides a parity generation circuit having a simplified circuit configuration.

The present invention uses a single input electrode, a single output electrode.

and a single b has a plurality of control electrodes, and a circuit means having a function of transmitting input electrode information to an output electrode according to control information given to the control electrode, and a circuit means having a function of interrupting a single r, as a component; The first circuit means is connected between the input terminal and the first output terminal, the second circuit means is connected between the second input terminal and the second output terminal, and the second circuit means is connected between the first input terminal and the second output terminal. The third circuit means is connected between the second output terminal, the fourth circuit means is connected between the second input terminal and the first output terminal, and the first and @2 circuit means are connected to each other. such that when the first and second circuit means are in the disconnected state, the third and fourth circuit means are in the disconnected state, and when the first and second circuit means are in the disconnected state, the third and fourth circuit means are in the transmitting state. A parity generation circuit is provided in which n stages (b: positive integer) of circuit units in which complementary data signals are input to control electrodes of respective circuit means are directly read in series.

Thanks to the great invention, a high-speed and simple logic configuration can be realized. If this parity generation circuit is applied to an integrated circuit device, it becomes possible to distribute the device in the layout, and the parity generation circuit on the chip can be realized. It becomes possible to reduce the area occupied by the

<Embodiment> FIG. 1 shows a first embodiment of a parity generation circuit according to the invention. 502. ．． 508, 504, 505 are circuit means, control input electrodes 506, 507, 508, respectively.
, 509, and conduction or non-conduction between the input and output terminals of the circuit means can be controlled by the polarity of the control signal.

In this embodiment, for convenience, in A, the circuit means is in a conductive state in response to a control input of logic "1", and logic "'O"
It shall be in a non-conducting state with respect to the control input.

The first circuit means 502 has a first input terminal 510 and a first
The second circuit means 503 is connected between the output terminals 512 of the
is connected between the second input terminal 513 and the second output terminal 514, and the third circuit means 504 is connected between the first input terminal 51
0 and the second output terminal 514, and the fourth circuit means 505 is connected between the second input terminal 513 and the first output terminal 512, forming a first circuit unit 501. Note that the control input electrodes 506 and 507 of the circuit means 502 and 503 receive data input signals. is input, and the control input type 1508,5 of the circuit means 504 and 505
A data input signal complementary to Do is input to 09.

In this embodiment, a case is shown in which four stages of the circuit units 501 are connected in series, and corresponding complementary data input signals Di, D are supplied to the second to fourth stage circuit units.
i (i=1 to 3) are connected using the same input method as in the first stage. The input terminal 510 of the first stage is connected to the power supply potential Vcc.
(corresponding to logic "1"), and the second input terminal 5]3 is connected to ground potential (corresponding to logic "0").

The parity output is the first output terminal 51 of the fourth stage circuit unit.
Parity output Po odder than 5: Also second output terminal 51
6, the even parity output Pe is output according to the truth value (Table 1) of the data input signal, respectively.

Next, the operation in an unimplemented example will be described in detail.

Focusing on the first stage circuit unit 501, the first input terminal is connected to the power supply potential VCC, and the second input terminal 501 is connected to the power supply potential VCC.
13 is connected to the ground potential, so when the first data input signal is logic "1"(Do""1",Do="O"), the one circuit means 502 and 503 become conductive and the one circuit is activated. Since the means 504 and 505 become non-conductive, the first input terminal information "1" is output to the first output terminal 512,
Similarly, second input terminal information "0" is output to the second output terminal 514.

Conversely, the first data input signal is logic ``0''CD.

= II Q n , D0 = II l″), the one-circuit means 502 and 503 are non-conductive and the one-circuit means 504 and 505 are conductive, so that the first output terminal 51
Information "1011" which is the opposite of the first input terminal information is output to the terminal 2, and similarly, information "1" which is the opposite of the second input terminal information is output to the second output terminal 514.

If the logic of the data input signal is ``l'', the input information is transmitted to the next stage as is, and if the logic of the data input signal is ``0'', information opposite to the input information is transmitted to the next stage. It turns out.

In the non-embodiment, the circuit unit 501 is connected in four stages, and therefore it is possible to generate a parity with a data length of 4 bits.

The reason why parity information is generated in the non-embodiment is as follows.

(1) Data input signal. −Logic “°l” in D3
If the number of ``0'' is an even number, the number of logic ``0'' is also an even number because the data length is 4 bits in the unimplemented example. Therefore, an even number of data inversions occur, and eventually the output terminal of the final stage is output. The same information as the input terminal of the first stage is output. (Po=”
l”, Pew”O”) (2) Data input signal D0~
When the number of logic ``171'' in D3 is odd, in this case the number of logic ``0'' is also odd. Therefore, an odd number of data inversions occur, and in the end, the output terminal of the final stage is connected to the first stage. Information opposite to the input terminal of is output. (Po=+Ion
, pe-tt s') As mentioned above, according to the invention, a parity generation circuit can be realized with a very simple circuit configuration, and even when the data length becomes long, the circuit units connected in series can be realized. In order to be able to respond simply by increasing the number.

No need for complex logic gates.

Due to the above-mentioned features, the present invention is very effective particularly when a parity generation circuit is built into an integrated circuit device, and is suitable for high integration.

Next, an embodiment will be described in which the invention is applied to a parity generation circuit inside an integrated circuit. That is, FIG. 2 shows a second embodiment in which the invention is applied inside a semiconductor memory device.

This example assumes a memory element with 8-bit parallel input/output and parity pits, M, )-M
, is a memory subarray having means for accessing particular bits therein.

110Q to 1107 are predetermined control means for controlling input/output of data of each sub-play information, and exist corresponding to each individual memory sub-array.

Qo-Qy is the above-mentioned circuit unit which is not yet invented.

Shodan Q. The first input terminal 601 of the circuit unit is connected to the power supply potential Vcc (logic "1'"), and the second input terminal 602 is connected to the ground potential (logic "°0"). are respectively connected by two trees of information transmission lines as in the first embodiment shown in FIG. Even parity is output.Furthermore, complementary data signals Di, Di (i=0 to 7) are inputted to each of the above circuit units from the control means corresponding to each circuit unit.

According to the embodiment of the youngest brother 2, each circuit unit can be placed close to its corresponding control means, and each circuit unit can be connected with only a 2-thick information transmission line, so that integration is possible. This enables extremely area-efficient wiring on the circuit.

Above 1. In the second embodiment, an even number of circuit units is provided, but the present invention is not limited to this. That is, the first input terminal of the circuit unit of the first stage receives the potential information of logic level "1", and the second input terminal receives the logic level "°".
When applying potential information of 0'', if the circuit unit is an even number of stages, an odd parity output is generated from the first output terminal of the final stage circuit unit, and an even parity output is generated from the second output terminal.

On the other hand, if one circuit unit has an odd number of stages, the first
An even parity output is generated from the second output terminal, and an odd parity output is generated from the second output terminal.

Here, various circuit configurations can be considered as the circuit means which is a component of the above-mentioned circuit unit.

FIG. 3 shows the components when an N-channel MOS transistor is applied as the circuit means, and the source 7'OI
is the input electrode, the drain 702 is the output electrode, and the gate 703
is made to function as a j+i control electrode.

FIG. 4 shows a third embodiment in which this MOS transistor is used as circuit means. The circuit operation in FIG. 4 is almost the same as the first embodiment shown in FIG.

In FIG. 5, the source of an N-channel MOS transistor 801 and the source of a P-channel MOS transistor 802 are commonly connected to form an input electrode 803.
) drain of transistor 801 and P channel MO5I-
The drains of the transistors are commonly connected as an output electrode 804, the gate of the N-channel MOS transistor 801 is used as the first control electrode 805, and the gate of the P-channel MOS transistor 802 is used as the second control electrode 806. FIG. 6 shows a fourth embodiment in which this circuit means is used. The circuit operation in FIG. 6 is also substantially the same as that in the first embodiment shown in FIG.

Furthermore, it is also possible to use a tri-state buffer circuit shown in FIG. 7 as the circuit means.

In this case, 901 is the input electrode and 902 is the output electrode.

903 functions as a control electrode, and when the control electrode 903 has logic +1171, the output electrode 902 outputs the same logic as the input electrode 901, and the control electrode 903 has logic 0
”, the output electrode 902 becomes high impedance.

By using this circuit as a component in FIG. 1, a parity generation circuit having a similar function can be realized.

Furthermore, as a modification of the embodiment @1 in FIG. 1, a fifth embodiment shown in FIG. 8 is also possible in which the polarities of the data input signals Di and Di (i=0 to 3), which are control signals, are reversed. be. The circuit operation is also almost the same as in FIG.

Various other embodiments are possible, and the circuits cited here are only some of the embodiments.

<Effects of the Invention> According to the present invention, a parity generation circuit can be realized with a very simple circuit configuration, and even when the data length becomes long, it can be handled simply by increasing the number of circuit units connected in series. , no need for complex logic gates.

In view of this, the present invention is very effective when incorporating a parity generation circuit into an integrated circuit, and can contribute to higher integration of integrated circuit devices.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a first embodiment according to the invention,
FIG. 2 is a block diagram showing a second embodiment in which the invention is applied to a semiconductor memory device, and FIG. 5 and 7 are diagrams showing examples of the components of a parity generation circuit according to the invention, FIGS. 4 and 6 are circuit diagrams showing third and fourth embodiments of the invention, and FIG. A block diagram showing a fifth embodiment according to the invention, and FIGS. 9 to 12 are conventional parity bit generation circuit diagrams. Po: Odd parity output, Pe: Even parity output. Di, Di (i=0 to 3): Complementary data input signal, 501: Circuit unit, 502°503, 504°50
5 = circuit means. Agent Patent attorney Takeshi Sugiyama (and 1 other person)'#511 1 to 711il yccDo I> [)2
r: hM℃ 1i 9 Figure

Claims (1)

[Claims] 1. A circuit means having a single input electrode, a single output electrode, and a control electrode is an element, and first, second, third, and fourth circuit means consisting of the circuit means The circuit means is controlled by a data signal applied to the control electrode and its inverted signal, and when the first and second circuit means are in a transmitting state, the third and fourth circuit means are in a disconnecting state, and the first and second circuit means are in a disconnecting state. When the second circuit means is in the cut-off state, the third and fourth circuit means are connected in a transmitting state to form a circuit unit, and the circuit units are connected in series at least as many times as the number of bits of the data signal. A parity generation circuit characterized by: 2) The parity generation circuit according to claim 1, wherein said circuit means comprises one MOS transistor. 3) The circuit means includes a PMOS transistor and an NMO transistor whose sources and drains are connected to each other.
2. The parity generation circuit according to claim 1, wherein the parity generation circuit comprises an S transistor. 4) The parity generation circuit according to claim 1, wherein the signal applied to the control electrode of each circuit unit consists of two lines: a 1-bit data signal line and its inverted signal line.