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JPS63152246U - - Google Patents

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Publication number
JPS63152246U
JPS63152246U JP4358787U JP4358787U JPS63152246U JP S63152246 U JPS63152246 U JP S63152246U JP 4358787 U JP4358787 U JP 4358787U JP 4358787 U JP4358787 U JP 4358787U JP S63152246 U JPS63152246 U JP S63152246U
Authority
JP
Japan
Prior art keywords
resin layer
phenol
semiconductor chip
integrated circuit
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4358787U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP4358787U priority Critical patent/JPS63152246U/ja
Publication of JPS63152246U publication Critical patent/JPS63152246U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本考案の第1の実施例の断面図、第2
図は本考案の第2の実施例の断面図、第3図は従
来の混成集積回路装置の一例の断面図である。 1…回路基板、2…半導体チツプ、3…ボンデ
イングワイヤ、4…フエノールプリコート樹脂層
、5…外部リード、6…外装樹脂層、7…耐熱性
テープ、8…熱収縮性テープ、9…気泡。
FIG. 1 is a sectional view of the first embodiment of the present invention;
The figure is a sectional view of a second embodiment of the present invention, and FIG. 3 is a sectional view of an example of a conventional hybrid integrated circuit device. DESCRIPTION OF SYMBOLS 1... Circuit board, 2... Semiconductor chip, 3... Bonding wire, 4... Phenol precoat resin layer, 5... External lead, 6... Exterior resin layer, 7... Heat resistant tape, 8... Heat shrinkable tape, 9... Bubbles.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 回路基板上に塔載した半導体チツプと、該半導
体チツプ上に被覆されたフエノールプリコート樹
脂層とを備える混成集積回路装置において、前記
フエノールプリコート樹脂層を覆つて密着するテ
ープを有することを特徴とする混成集積回路装置
A hybrid integrated circuit device comprising a semiconductor chip mounted on a circuit board and a phenol precoat resin layer coated on the semiconductor chip, characterized by comprising a tape that covers and adheres to the phenol precoat resin layer. Hybrid integrated circuit device.
JP4358787U 1987-03-24 1987-03-24 Pending JPS63152246U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4358787U JPS63152246U (en) 1987-03-24 1987-03-24

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4358787U JPS63152246U (en) 1987-03-24 1987-03-24

Publications (1)

Publication Number Publication Date
JPS63152246U true JPS63152246U (en) 1988-10-06

Family

ID=30860584

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4358787U Pending JPS63152246U (en) 1987-03-24 1987-03-24

Country Status (1)

Country Link
JP (1) JPS63152246U (en)

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