JPS6284970U - - Google Patents
Info
- Publication number
- JPS6284970U JPS6284970U JP1985176360U JP17636085U JPS6284970U JP S6284970 U JPS6284970 U JP S6284970U JP 1985176360 U JP1985176360 U JP 1985176360U JP 17636085 U JP17636085 U JP 17636085U JP S6284970 U JPS6284970 U JP S6284970U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- wiring
- wiring conductor
- resin film
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Structure Of Printed Boards (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
Description
第１図ａは本考案の一実施例の平面図、第１図
ｂは第１図ａに示す実施例のＡ―Ａ′線断面図、
第２図ａは従来の混成集積回路の一例の平面図、
第２図ｂは第２図ａに示す混成集積回路のＢ―Ｂ
′線断面図である。
１，１′……回路基板、２……半導体チツプ、
３……導体ペースト、４，４′……配線導体、５
……ボンデイングワイヤ、６……樹脂膜、７……
チツプ部品、８……外部端子、９……はんだ、１
０……配線導体、１１……絶縁ガラス。
FIG. 1a is a plan view of an embodiment of the present invention, FIG. 1b is a sectional view taken along line A-A' of the embodiment shown in FIG. 1a,
FIG. 2a is a plan view of an example of a conventional hybrid integrated circuit;
Figure 2b shows the B-B of the hybrid integrated circuit shown in Figure 2a.
FIG. 1, 1'... circuit board, 2... semiconductor chip,
3... Conductor paste, 4, 4'... Wiring conductor, 5
...Bonding wire, 6...Resin film, 7...
Chip parts, 8...External terminal, 9...Solder, 1
0... Wiring conductor, 11... Insulating glass.
Claims (1)
体チツプの配線用パツドに接続される前記回路基
板に設けられた配線導体と、前記半導体チツプ及
び配線導体を覆つて形成される樹脂膜とを備える
混成集積回路において、前記樹脂膜に覆われた前
記配線導体の少くとも１部を多層配線としたこと
を特徴とする混成集積回路。 A semiconductor chip mounted on a circuit board, a wiring conductor provided on the circuit board connected to a wiring pad of the semiconductor chip, and a resin film formed to cover the semiconductor chip and the wiring conductor. A hybrid integrated circuit, wherein at least a portion of the wiring conductor covered with the resin film is a multilayer wiring.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985176360U JPS6284970U (en) | 1985-11-15 | 1985-11-15 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985176360U JPS6284970U (en) | 1985-11-15 | 1985-11-15 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6284970U true JPS6284970U (en) | 1987-05-30 |
Family
ID=31116530
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985176360U Pending JPS6284970U (en) | 1985-11-15 | 1985-11-15 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6284970U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01119047A (en) * | 1987-10-30 | 1989-05-11 | Nec Corp | Integrated circuit device |
-
1985
- 1985-11-15 JP JP1985176360U patent/JPS6284970U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01119047A (en) * | 1987-10-30 | 1989-05-11 | Nec Corp | Integrated circuit device |