JPS63146451A - Formation of interconnection pattern - Google Patents
Formation of interconnection patternInfo
- Publication number
- JPS63146451A JPS63146451A JP25411386A JP25411386A JPS63146451A JP S63146451 A JPS63146451 A JP S63146451A JP 25411386 A JP25411386 A JP 25411386A JP 25411386 A JP25411386 A JP 25411386A JP S63146451 A JPS63146451 A JP S63146451A
- Authority
- JP
- Japan
- Prior art keywords
- photoresist
- plating
- forming
- metal layer
- layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000015572 biosynthetic process Effects 0.000 title 1
- 239000002184 metal Substances 0.000 claims abstract description 30
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 30
- 238000007747 plating Methods 0.000 claims abstract description 25
- 238000005530 etching Methods 0.000 claims abstract description 12
- 239000004065 semiconductor Substances 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 238000009713 electroplating Methods 0.000 claims abstract description 5
- 238000000034 method Methods 0.000 claims description 15
- 238000004544 sputter deposition Methods 0.000 claims description 2
- 238000007740 vapor deposition Methods 0.000 claims description 2
- 239000011248 coating agent Substances 0.000 claims 3
- 238000000576 coating method Methods 0.000 claims 3
- 238000000206 photolithography Methods 0.000 claims 3
- 238000004519 manufacturing process Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000002411 adverse Effects 0.000 description 2
- 230000003746 surface roughness Effects 0.000 description 2
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、半導体基板上への微細配線パターン形成方
法、特に、エアブリッジの形成方法に関するものである
。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for forming a fine wiring pattern on a semiconductor substrate, and particularly to a method for forming an air bridge.
(従来の技術)
第2図(a)〜(h)は、従来の半導体基板上への橋状
の立体的金属微細配線パターン(エアブリッジ)形成方
法の一例の主要製造工程順序を示す要部破断断面図で、
以下、これを用いて従来の方法を説明する。(Prior Art) Figures 2(a) to 2(h) show main parts showing the main manufacturing process sequence of an example of a conventional method for forming a bridge-like three-dimensional metal fine wiring pattern (air bridge) on a semiconductor substrate. In the broken cross-sectional view,
Hereinafter, the conventional method will be explained using this.
第2図において、lは半導体基板、2及び22はそれぞ
れ第1/第2のフォトレジスト層。In FIG. 2, 1 is a semiconductor substrate, 2 and 22 are first and second photoresist layers, respectively.
3はめっき給電金属層、4はめっき金属層である。3 is a plating power supply metal layer, and 4 is a plating metal layer.
次に製造工程順序について説明する。Next, the manufacturing process order will be explained.
まず、第2図(a)に示すように、半導体基板1上に第
1のフォトレジスト2を塗布・バターニングし、次に、
航記フォトレジストパターン上に、蒸着又はスパッタリ
ングによって、めっき給電金属層3を形成する(第2図
(b))、続いて第2のフォトレジスト22を塗布(第
2図(C))、バターニングし、第2図(d)に示すよ
うな橋状の立体的なレジストぬき部分を形成する。First, as shown in FIG. 2(a), a first photoresist 2 is coated and patterned on a semiconductor substrate 1, and then,
A plating power supply metal layer 3 is formed on the photoresist pattern by vapor deposition or sputtering (FIG. 2(b)), and then a second photoresist 22 is applied (FIG. 2(C)). Then, a bridge-like three-dimensional resist-free portion is formed as shown in FIG. 2(d).
次に、電解めっきを行って前記レジストぬき部分にのみ
選択的にめっき金属層4を成長させ(第2図(e))、
その後、第2のフォトレジスト層22の除去、めっき給
電金属層3の不要部分、第1のフォトレジスト層2の除
去を順次行い(第2図(f)〜(h))、エアブリッジ
を得るようなパターン形式方法が行われていた。Next, electrolytic plating is performed to selectively grow a plating metal layer 4 only in the resist-free areas (FIG. 2(e)),
Thereafter, the second photoresist layer 22, the unnecessary portion of the plating power supply metal layer 3, and the first photoresist layer 2 are sequentially removed (FIG. 2(f) to (h)) to obtain an air bridge. A similar pattern format method was used.
しかしながら、以上のような従来の微細配線パターン形
成方法によると、電解めっき後、めっき給電金属3の不
要部分のエツチングを行う工程(第2図(g))におい
て、めっき金属層4表面もエツチングされ1口減りや表
面荒れを生ずる。However, according to the conventional method for forming fine wiring patterns as described above, the surface of the plating metal layer 4 is also etched in the step of etching unnecessary parts of the plating power supply metal 3 after electrolytic plating (FIG. 2(g)). This will cause loss of bite and surface roughness.
特に、ライン幅が1〜2μmの微細エアブリッジにおい
ては、上記めっき金属層4の目減りや表面荒れ配線の外
観のみならず、強度にも悪影響を与えるなどの問題点が
あった。In particular, in the case of fine air bridges having a line width of 1 to 2 .mu.m, problems arise such as not only the thinning of the plated metal layer 4 and the roughened surface of the wiring, but also the appearance of the wiring, which also adversely affects the strength.
この発明は、上記の様な従来方法の問題点にかんがみて
なされたもので、外観が良好でかつ目的としている強度
の安定した微細エアブリッジを再現性良く得る方法を提
供することを目的としている。This invention was made in view of the problems of the conventional methods as described above, and aims to provide a method for obtaining fine air bridges with good appearance and stable strength with good reproducibility. .
このため、この発明に係る微細配線パターン形成方法に
おいては電解めっき工程、第2のフォトレジスト除去工
程の次に、めっき金属層部分を被覆する様な第3のフォ
トレジストパターンを形成し、その後、めっき給電層不
要部分のエツチング除去を行う様にすることにより、前
記目的を達成しようとするものである。Therefore, in the method for forming a fine wiring pattern according to the present invention, after the electrolytic plating step and the second photoresist removal step, a third photoresist pattern that covers the plating metal layer portion is formed, and then, The above objective is achieved by etching away unnecessary portions of the plating power supply layer.
以上のようなこの発明方法によれば、めっき金属層部分
を選択的に被覆するように形成した第3フオトレジスト
パターンは、めっき給電層不要部分のエツチング除去工
程におけるめっき金属層表面のエツチングにより目減り
や表面の荒れ等を防ぐことができる。According to the method of the present invention as described above, the third photoresist pattern formed to selectively cover the plated metal layer portion is reduced due to the etching of the surface of the plated metal layer during the etching removal process of the unnecessary portion of the plated power supply layer. This can prevent surface roughness, etc.
(実施例〕 以下に、この発明を、実施例に基づいて説明する。(Example〕 The present invention will be explained below based on examples.
第1図(a)〜(f)は、この発明の一実施例の微細配
線パターン形成方法における主要製造工程順序を示す要
部の各破断断面図で、前記従来例第2図(a)〜(h)
におけると同一(相当)構成要素は同一記号で表す。1
は半導体基板、2及び222は、それぞれ第17第3フ
オトレジスト層、3はめっき給電金属層、4はめっき金
属層である。FIGS. 1(a) to 1(f) are cutaway sectional views of main parts showing the sequence of main manufacturing steps in a fine wiring pattern forming method according to an embodiment of the present invention, and FIGS. 2(a) to 2(f) of the conventional example (h)
The same (equivalent) components as in are represented by the same symbols. 1
2 and 222 are respectively the 17th and 3rd photoresist layers, 3 is a plating power supply metal layer, and 4 is a plating metal layer.
第1rA(a)は、第2図(f)と同様の工程状態を示
し、この実施例方法においては、この状態の後、第1図
(b)に対ように、第3のフォトレジスト222を塗布
バターニングし、めっき金属層4部分を選択的に被覆す
る。次に、第1図(C)のように、めっき給電金属層3
の不要部分をエツチング除去し、続いて第1のフォトレ
ジスト層2を除去して、第1図(d)にその外観を示す
ようなエアブリッジを得るようにしたものであり、第1
図(c)におけるめっき給電金属層3の不要部分除去の
ためのエツチングの際、めっき金属層4は、表面液Tf
1/保護されているため、エツチングによる悪影響を受
けることがない。この効果は、例えば、ライン幅が1〜
2μm程度の微細なエアブリッジを形成する場合に特に
効果的である。1rA(a) shows a process state similar to that in FIG. 2(f), and in this embodiment method, after this state, as in FIG. 1(b), the third photoresist 222 is coated and patterned to selectively cover the four portions of the plating metal layer. Next, as shown in FIG. 1(C), the plating power supply metal layer 3
The unnecessary portions of the photoresist layer 2 are removed by etching, and the first photoresist layer 2 is then removed to obtain an air bridge as shown in FIG. 1(d).
During etching to remove unnecessary parts of the plating power supply metal layer 3 in FIG.
1/Since it is protected, it will not be adversely affected by etching. This effect can be achieved, for example, when the line width is 1~
This is particularly effective when forming fine air bridges of about 2 μm.
以t、説明したようにこの発明、によれば、めっき給電
金属層の不要部分をエツチング除去を行う工程において
、めっき金属層表面のエツチングを防止でき、外観が良
好で、かつ強度の安定した工アブリッジを再現性良く得
られる効果がある。As described below, according to the present invention, it is possible to prevent etching of the surface of the plated metal layer in the process of etching away unnecessary portions of the plated power supply metal layer, and to produce a workpiece with a good appearance and stable strength. It has the effect of obtaining a bridge with good reproducibility.
第1図(a)〜←瞬は、この発明の一実施例の微細配線
パターン形成方法における主要製造工程順序を示す要部
各破断断面図、第2図(a)〜(h)は、従来法の一例
の製造工程順序を示す要部各破断断面図である。Figures 1(a) to ← are cutaway cross-sectional views of main parts showing the sequence of main manufacturing steps in a fine wiring pattern forming method according to an embodiment of the present invention, and Figures 2(a) to (h) are conventional FIG. 3 is a fragmentary cross-sectional view of each main part showing the order of manufacturing steps in an example of the method.
1:半導体基板 2.22,222:第1/第2/第3フオトレジスト層 3:めっき給電金属層 4:めっき金属層1: Semiconductor substrate 2.22, 222: First/second/third photoresist layer 3: Plated power supply metal layer 4: Plated metal layer
Claims (1)
、半導体基板表面に第1のフォトレジスト層を塗布形成
する工程と、写真製版によりエアブリッジの橋桁がくる
位置にぬき部分を有する前記第1のフォトレジストのパ
ターンを形成する工程と、前記形成されたパターン上に
蒸着又はスパッタリングによりめっき給電金属層を形成
する工程と、前記めっき給電金属層上に第2のフォトレ
ジスト層を塗布形成する工程と、前記第1のフォトレジ
ストのぬきパターン部分の少くとも2つを線状に結ぶ範
囲がぬき部分となった前記第2のフォトレジストのパタ
ーンを写真製版により形成する工程と、前記第2のフォ
トレジストパターンをマスクとして電解めっきを行う工
程と、前記第2のフォトレジストを除去する工程と、第
3のフォトレジスト層を塗布形成し、写真製版によりめ
っきパターンのある部分にのみ前記第3のフォトレジス
ト層を残す工程と、前記めっき給電金属の不要部分層を
エッチング除去する工程と、第1のフォトレジスト層を
除去してエアブリッジを得る工程とを含むことを特徴と
する配線パターン形成方法。In the step of forming an air bridge on the surface of a semiconductor substrate, a step of coating and forming a first photoresist layer on the surface of the semiconductor substrate, and a step of forming a first photoresist layer by photolithography at a position where the bridge girder of the air bridge is located, forming a plating power supply metal layer on the formed pattern by vapor deposition or sputtering; coating and forming a second photoresist layer on the plating power supply metal layer; forming, by photolithography, a pattern of the second photoresist in which a range linearly connecting at least two of the cut-out pattern portions of the first photoresist becomes the cut-out portion; a step of performing electrolytic plating using the second photoresist as a mask, a step of removing the second photoresist, and a step of coating and forming a third photoresist layer, and applying the third photoresist layer only to the portion where the plating pattern is provided by photolithography. A method for forming a wiring pattern, the method comprising: a step of etching away an unnecessary partial layer of the plating power supply metal; and a step of removing the first photoresist layer to obtain an air bridge.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25411386A JPS63146451A (en) | 1986-10-23 | 1986-10-23 | Formation of interconnection pattern |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25411386A JPS63146451A (en) | 1986-10-23 | 1986-10-23 | Formation of interconnection pattern |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS63146451A true JPS63146451A (en) | 1988-06-18 |
Family
ID=17260404
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP25411386A Pending JPS63146451A (en) | 1986-10-23 | 1986-10-23 | Formation of interconnection pattern |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS63146451A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0517551A2 (en) * | 1991-06-06 | 1992-12-09 | Nec Corporation | Method of forming a multilayer wiring structure on a semiconductor device |
-
1986
- 1986-10-23 JP JP25411386A patent/JPS63146451A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0517551A2 (en) * | 1991-06-06 | 1992-12-09 | Nec Corporation | Method of forming a multilayer wiring structure on a semiconductor device |
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