JPS63142657A - Gate array incorporating test circuit - Google Patents

Abstract

PURPOSE:To obtain a gate array which can be operated normally both during a test and during an ordinary operation by installing a flip-flop or a latch circuit for latching an input signal and is composed of a control circuit for controlling the flip-flop or the latch circuit. CONSTITUTION:After a control signal at a control pin H has been fixed to a HIGH level and an input signal has been made to pass through a D flip-flop F, input signals for test use are input to input pins A1, B1. After the control signal at a control pin G has been changed to a LOW level at a transition point of the input pins A1, B1 and the input signals have completed their transition, the control signal rises to the HIGH level. The D flip-flop F latches the input signals at the rise of this control signal and is transmitted to an output; as a result, the input signals become uniform at the transition point when the control signal at the control pin G rises, and are transmitted to output pins A2 and B2. If the control signal at the control pin H is fixed to the LOW level, the input signals at the input pins A1, B1 are transmitted to the output pins A2, B2 as they are, and a test circuit does not exert any bad influence upon the actual operating state.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuits, and particularly to gate arrays.

rPrior Art] Conventionally, no special test circuit has been built into a gate array.

[Problem that the invention seeks to solve]

In the conventional gate array described above, if an attempt is made to realize a circuit configuration as shown in FIG. 5, change the input signal B, and latch the changed logic signal into the flip-flop F using the signal A, the signal A and signal B must be changed at least simultaneously. (Signal B must not change later than signal A.) When testing a gate array with such a circuit configuration,
In consideration of the above, the test equipment is programmed to change signal A and signal B simultaneously. However, due to variations in operating time for each pin of the signal generation part of the test equipment (hereinafter referred to as pin-to-pin skew), even though signals A and B are programmed to change at the same time, changes in signal B do not occur. It may happen that the change in signal A is delayed.

When such a situation occurs, although the circuit operates normally in actual use, it does not operate normally during testing. To avoid this, signal A must be changed to signal B.
It would be possible to program the test equipment so that it changes more slowly, but it is extremely difficult to judge and program which signals should be input early and which signals should be delayed among the large number of input signals. However, if the timing relationship between the signals is very complex, it may not be possible to program them completely.

As mentioned above, since the conventional gate array does not have a test circuit, it has the problem that a normal test may not be possible.

SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above-mentioned problems and provide a gate array having a test circuit that operates normally both during testing and during operation.

[Means for solving problems]

The configuration of the gate array of the present invention is characterized by having a test circuit consisting of a flip-flop or latch circuit that latches an input signal and a control circuit that controls these flip-flops or latch circuits.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is an example of a circuit diagram of a test circuit portion of a gate array having a test circuit according to a first embodiment of the present invention constructed using D flip-flops.

A1. B1 is an input pin for input signals and is connected to an external terminal. A2. B2 is an output pin for the output signal of the test circuit, and is connected to the gate array internal circuit 1. F is a D flip-flop, HlG is a control pin for inputting a control signal for the D flip-flop F, and is connected to an external terminal.

The operation of this test circuit is as follows.

(1) Fix the control signal on the control pin H to a high level so that the input signal passes through the D flip-flop F.

(2) Input pins A, B for input signals for testing.

Enter.

3) Input pin A 1. At the change point of B l,
At about the same time, the control signal on the control pin G is changed to a low level, and after the input signals on the input pins A, , B are completed changing, they are raised to a high level. D flip-flop F
latches the input signal at the rising edge of the control signal at the control signal input pin G and transmits it to the output, so the timing chart is as shown in FIG.

(4) By the operations (1) to (3), input bins A1 and B are
The input signal No. 1 is transmitted to the output pins A2 and 82 with the change points aligned at the rising edge of the control signal on the control pin G.

(5) In actual use, if the control signal on control pin H is fixed at a low level, the input signals on input pins A, , B remain unchanged on output pins A2, . Since the signal is transmitted to B2, this test circuit will not cause any adverse effects in actual use.

In this circuit, it is only necessary to sufficiently delay the rising timing of the control signal on the control pin G with respect to changes in all input signals, and it is extremely easy to program such timing into the test equipment.

FIG. 3 is a second example of a circuit diagram of a test circuit portion of a gate array having a test circuit according to a second embodiment of the present invention constructed using a simple latch circuit.

A 1 and B 1 are input pins for input signals, and are connected to external terminals. A 2 and B 2 are output pins for output signals of the test circuit, and gate array internal circuit 1
It is connected to the. G is a control pin that inputs a control signal for the latch circuit, and is connected to an external terminal.

The operation of this test circuit is as follows.

(1) Input pins A, B for input signals for testing.

Enter.

(2) At the change point of the input signals of input pins A1, Bl, after the input signals of input pins A, B, have completed changing, the control signal of control pin G is raised to high level, and after a while Then lower it to low level. In the latch circuit, when the control signal on the control pin G becomes high level and the previous stage transfer gate opens, the input pins A I and B
1 is transmitted as it is to output pins A 2 and B 2, but when the control signal of control pin G becomes low level and the previous transfer gate closes, the input signal of input pin A
1. Regardless of the change in the input signal of B I, the input signal at the time when the control signal of control pin G falls is maintained, so the timing chart at this time is as shown in FIG. 4.

(3) By the operation of (1) to 3), input pins A, B
, the input signals of the output pins A2 . It is transmitted to B2.

(4) In actual use, if the control signal on the control pin G is fixed at a high level and the transfer gates before and after the latch circuit are always open, the input signals on the input pins A, , B can be directly transferred to the output pin A2. .

It can be transmitted to B2.

The second embodiment has an advantage over the first embodiment in that only one signal is required to control the test circuit, but on the other hand, since the latch circuit is directly inserted into the input signal line, the input signal There is a disadvantage that the time for the change in to be transmitted to the internal circuit is slightly delayed, but this is not a particular problem.

〔Effect of the invention〕

As explained above, according to the present invention, there is an effect that a gate array that can be easily tested can be constructed without considering pin-to-pin skew during testing.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a test circuit portion of a gate array having a test circuit according to a first embodiment of the present invention configured using D flip-flops, and FIG. 2 is a diagram when the test circuit of FIG. 1 is operated. Figure 3 is a circuit diagram of the test circuit portion of the second embodiment using a simple latch circuit, Figure 4 is a timing chart when Figure 3 is operated, Figure 5 is a conventional circuit diagram. This is an example of a circuit diagram that may interfere with testing in a gate array. A, B, AI, Bt...input pin, C, A2. B2
...Output to the inside of the gate array, E...Inverter, F...Flip-flop, G, H...Input pin for test circuit control signal, 1...Gate array internal circuit. Iwa 2 map

Claims (1)

[Claims] A gate array comprising a test circuit comprising a flip-flop or latch circuit that latches an input signal and a control circuit that controls the operation of these flip-flops or latch circuits.