JPH0210176A - Semiconductor integrated circuit having test terminal - Google Patents

Abstract

PURPOSE:To execute an access from the outside of many test points by a small number of external terminals by providing a shift register for shifting the data in a shape of a ring, and a flip-flop whose output state is varied, in accordance with a signal from the outside. CONSTITUTION:A shift register 17 shifts data which is held in a shape of a ring and outputs it to flip-flops 18-21 in accordance with a clock signal CK inputted from the outside. Subsequently, the flip-flops 18-21 are provided in accordance with each bit of a parallel output of the shift register 17, and vary its output state in accordance with a toggle signal TG inputted from the outside. A decoder 22 inputs this output in accordance with an enable signal ENB inputted from the outside, and access from the outside can be executed against the corresponding test point XJ. In such a way, the fault detection rate can be improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] In order to increase the fault detection rate of a gate array, the present invention provides a semiconductor device having a test terminal that allows external access to any test point of an integrated circuit. Concerning integrated circuits.

[Prior Art] Conventionally, in order to improve the failure detection rate of gate arrays, a terminal is provided outside the integrated circuit, and a signal input from this test terminal is used to test the integrated circuit (LSI).
) A circuit is known that allows access to any internal Nasu l-point from the outside.

FIG. 6 shows an example of this type of LSI. LSll is used as an external terminal in addition to the normal gate array input/output pin 2.
Equipped with STI terminal 3 and TEST2 terminal 4, these TE
For example, through the STI terminal 3 and the TEST2 terminal 4,
Test points 6 (Xo, X
+ ) was designed to supply a reset pulse independently.

[Problems to be Solved by the Invention] However, the above-described conventional LSI with test terminals has a problem in that as the number of test points increases, the number of test terminals to be provided also increases. Originally, the input/output pins of a gate array exist to transmit its original function to the outside. Therefore, it is not preferable to provide a large number of external terminals for internal testing. Also,
The procedure for setting up access to the test points of the target gate array must be minimized as much as possible.

The present invention has been made in view of such problems, and includes:
Enables external access to a large number of test points with fewer external test terminals and fewer procedures.
An object of the present invention is to provide a semiconductor integrated circuit having a test terminal that can further improve the failure detection rate.

[Means for Solving the Problems] A semiconductor integrated circuit according to the present invention stores at least two test external terminals and data in which one bit is in a first state and the other bits are in a second state. A shift register that shifts the data in a ring shape according to a clock signal input through the test external terminal, and a shift register provided corresponding to each bit of the parallel output of this shift register, which is input through the test external terminal. The parallel output of the shift register is input according to the toggle signal, and if the input is in the first state, the output is inverted, and if the input is in the second state, the output is held by a plurality of flip-flops and the outputs from these flip-flops are input. The present invention is characterized by comprising means for inputting an enable signal inputted through the external terminals for the above-mentioned eggplants 1 to 1 to enable external access to the test points inside the corresponding integrated circuit.

[Function] In the present invention, when a clock signal is input through the external test terminal, the position of the first state of the data held in the shift 1 register changes, and this first state is transferred to any flip-flop. can be given as input.

The flip-flop to which the first state is input changes its output state in response to a toggle signal input from an external test terminal. Therefore, by appropriately combining the shift operation of the shift register and the toggle operation of the flip-flop, an arbitrary output state of the flip-flop can be externally set with a small number of operations.

Based on the output of this flip-flop, a predetermined test point can be accessed from the outside.

According to the present invention, the number of test points is determined by the number of output bits of the flip-flop, and the output can be set by an external shift operation, so that only a small number of external terminals are required. Therefore, a large number of test points can be accessed from the outside with a small number of external terminals and a small number of operations.

[Examples] Examples of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a part of an LSI with test terminals according to an embodiment of the present invention.

This LSI is provided with a TESTI terminal 11 and a TEST2 terminal 12 as external terminals for testing in addition to normal gate array input/output pins (not shown). TEST1 terminal 1
1 and TEST2 terminals 12 are connected to an inverter] 3 and two AND gates 14 and 15 inside the LSI, depending on the supply form of this signal.
are converted into a clock signal CK, a toggle signal TG, and an enable signal ENB by a logic circuit Y[ consisting of a clock signal CK, a toggle signal TG, and an enable signal ENB.

The clock signal CK is applied to the shift clock terminal C of the 4-bit shift register 17.

As shown in FIG. 2, the initial values of the shift register 17 are such that only the output Qo is 1''' (first state) and the output Qo is 1''' (first state).
+ to Q3 hold data of "'O" (second state), and transmit the data to Q according to the clock signal CK. -+Q1
→Q2−→Q3→Qo. Shift register parallel outputs Qo to Q
3 are JK flip-flops 18, 19, 20.21 respectively
are given to the terminals of each J. The initial values of the outputs Ro to R3 of the JK flip-flops 18 to 21 are all 0'' as shown in FIG. C(
Even if the toggle signal TG is applied to the clock) terminal, its output R does not change, but if the toggle signal TG is input to the C terminal with 1'' applied to the J and J terminals, its rising edge will change. The outputs R8 to R5 of these JK flip-flops 18 to 21 are respectively inverted by the inputs A3 to Ao of the decoder 22.
is given to.

The decoder 22 has A3, A2, A1 . When AO is input, the binary value A3. A2. If we set Ao=j, enable signal E is applied to test point 23 (XJ >
When N=1, output 1. Test point 23 (
Xj (j=0 to 15) is connected, for example, to the Re5et or set terminal of a flip-flop inside the gate array, and one pulse of positive polarity is added to XJ (j=o to 15). and the flip-flops connected thereto are independently reset 1~ or cell 1~.

FIG. 5 shows an example of the operation of this circuit. First, the outputs of the JK flip-flops 18 to 21 R6, R1°R2, R3=
Therefore, when one pulse is input to the TEST2 terminal 1.2 while the TEST1 terminal 11 is 1'', the enable signal ENB is given to the Korg 22, and the A
o, , A, +' A2. A.

- A pulse synchronized with the first pulse is generated at the output (Xo) decoded from "0". This pulse allows a pulse to be applied independently to the test point +Xo.

Next, set TESTI terminal]1 to '0'' and connect TEST2.
When three serial pulses are applied to the terminal 12, these are applied as the clock signal CK to the shift 1 register, and its initial value Qo - "1", Q+ to Q3 = "0"
" is cyclically shifted and becomes Q3 = "1", Qo to Q2 - "O". Here, when the signal at the TESTI terminal 11 rises, the JK flip-flops 19 to 21
maintains its output R8 to R2="O"', and the JK flip-flop 18 changes its output R3 from '0" to '1".
invert it. As a result, the input A3 of the decoder 22
, A2, A1. A.

-"0001", and when the enable signal ENB is applied, a pulse can be output to the test point X1. Thereafter, by similarly supplying arbitrary pulses to the TESTI terminal 11 and the TEST2 terminal 12, the output states of the JK flip-flops]8 to 21 can be arbitrarily set.
It is possible to contribute to the internal inspection of the LSI by applying pulses independently to the LSI.

Note that the present invention is not limited to the embodiments described above. For example, in the above embodiment, the logic circuit 16 is provided and two
2 external terminals (TESTI terminal 11, TEST2 terminal 1
2) Three signals CK, E depending on the method of applying pulses to
Obtained NB and TG. Although this makes it possible to further reduce the number of external terminals, the above three signals may be inputted separately from the three external terminals. Although an example has been shown in which pulses are input from the outside to test points 1 to 1 to It can also be applied to inspections that read externally. In this case, a multiplexer may be used instead of the decoder 22.

[Effects of the Invention] As described above, according to the present invention, the output state of a flip-flop can be arbitrarily changed from the outside with a small number of operations by appropriately combining the shift register operation and the flip-flop toggle operation. Can be set. The number of available outputs is determined by the number of stages of the shift register and the number of output hits of the flip-flops, and these outputs can be set by an external shift operation. Therefore, it is possible to access many test points from the outside with a small number of external terminals and a small number of operations, which has the effect of increasing the failure detection rate.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main part configuration of an LSI with a test terminal according to an embodiment of the present invention, FIG. 2 is a diagram showing the initial state of a shift register in the same LSI, and FIG.
FIG. 4 is a diagram showing the initial state of the JK flip-flop in the same JK flip-flop, and FIG.
Figure 5 is an operating waveform diagram of the same LSI, and Figure 6 is a diagram of the conventional dess I.
FIG. 2 is a block diagram showing a one-terminal dominant LSI. 1; LSI, 2; Gate array input/output pin, 3゜11;
TESTI terminal, 4, 12. TES"F2 terminal, 5; gate array, 6.23; test point), 16; logic circuit, 7; shift 1 to register, 18 to 21; JK flip-flop, 22: decoder

Claims (1)

[Claims] (1) At least two external terminals for testing, storing data in which one bit is in the first state and the other bits are in the second state, and the above-mentioned data is stored in accordance with a clock signal inputted through the external terminals for testing. A shift register that shifts the data in a ring shape, and a toggle signal provided corresponding to each bit of the parallel output of this shift register and inputted through the external terminal for testing, inputting the parallel output of the shift register, and inputting the parallel output of the shift register. A plurality of flip-flops whose outputs are inverted when in the first state and held when in the second state, and the outputs from these flip-flops are inputted by an enable signal inputted through the external terminal for testing. What is claimed is: 1. A semiconductor integrated circuit having a test terminal, characterized in that the semiconductor integrated circuit is provided with means for enabling external access to a test point inside the corresponding integrated circuit.