JPS63128759A - Junction field effect transistor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

Detailed Description of the Invention [Summary] The present invention provides a junction field effect transistor in which a low impurity concentration or undoped InP gate layer is formed on an n-type InGaAs channel layer, and the gate By forming a p+ type InP gate region by diffusing Zn into the layer, strict control of Zn diffusion is not necessary, and mesa etching of the gate layer and the gate BJI region is ensured on the surface of the channel layer. As a result, the characteristics were significantly improved.

[Industrial application field]

The present invention relates to optical integrated circuits (optoelectronic integrated circuits).
integrated circuit:0EI
G) relates to a junction field effect transistor suitable for incorporation into a transistor.

[Conventional technology]

In recent years, research and development of 0BIC has been active, and it goes without saying that the semiconductor electronic device to be incorporated into it will be one that uses a compound semiconductor as a material in view of the balance with the semiconductor optical device. Since the speed must be increased, it is necessary to satisfy conditions such as operating in a wavelength range with high carrier mobility and low loss due to the optical transmission path.
/ InP/InGa than A I Ga As system
There is a tendency to use As-based materials.

FIG. 2 is a cross-sectional side view of a typical junction field effect transistor used in a conventional 0EIC.

In the figure, 1 is a semi-insulating InP substrate, 2 is an n-type InG substrate
3 is a p+ type 1 nGaAs gate layer, 4 is a gate electrode, 5 is a source electrode, 6 is a drain electrode, and 7 is a gate electrode.

Examples of the main data of each part are as follows.

+1) Thickness of channel layer 2: 0.2 Cμm] Impurity concentration: I x 101? (cm-3) (2
) Thickness of gate layer 3: 0,2 (μm) Impurity: Zn Impurity concentration: > I x 101 days (cm-”) (3
) About gate electrode 4 Material: A u / P t / Ti Thickness: 250
0 (person) / 200C person) / 300 [person] (4) Source electrode 5 and drain electrode 6 material: Au
/AuGe Thickness: 2700 [people] / 300 (people) (5) Gate electrode 7 Material: Same as source electrode 5 and drain electrode 6 Thickness: Same as source electrode 5 and drain electrode 6 Junction type field effect described above When manufacturing transistors, semi-insulating In
An n-type InGaAs channel layer 2 is formed on a P substrate 1 to a thickness of 0.
4 [μm], and diffused Zn into the n-type InGaAs channel layer 2 to a depth of 0.2 (μm) to form a p+ type 1
An nGaAs gate layer 3 is formed, a gate electrode 4 is formed on the gate layer 3, and a part of the surface of the channel layer 2 is etched by mesa etching and side etching of the gate layer 3 using the gate electrode 4 as a mask. After exposing, a gate electrode 5 and a drain electrode 6 are formed. Note that at this time, the gate electrode 4 is covered with the gate electrode 7.

[Problem that the invention seeks to solve]

As mentioned above, when manufacturing the transistor shown in FIG. 2, Zn is diffused into the channel layer 2 to form the gate layer 3, but the controllability when diffusing this Zn is very poor. When performing mesa etching on such a p+ type InGaAs layer, controllability is also poor because the underlying layer is the same InGaAs layer.

The present invention eliminates the influence of Zn diffusion even if there is a controllability problem, or solves the controllability problem that exists in mesa etching. Thus, a junction field effect transistor with good characteristics can be obtained.

[Means for solving problems]

In the junction field effect transistor according to the present invention,
n formed on a substrate (e.g. semi-insulating! nP substrate 1)
A channel layer (for example, n-type InGaAs channel layer 2) made of type InGaAs;
An InP gate layer (for example, n'' type InP gate layer 8) formed on the As channel layer and having a lower impurity concentration than the As channel layer, and a p+ type InP gate formed by diffusing Zn into the InP gate layer. region (for example, p+ type InP gate region 9).

[Effect]

By adopting the above structure, strict control of Zn diffusion during manufacturing is not required, and even if the control of Zn diffusion is poor and an InP gate layer remains on the n-type InGaAs channel layer, In the operating state, the InP gate layer is depleted, so there is no problem at all, and the mesa etching of the gate layer and gate region can be reliably stopped at the surface of the channel layer, and as a result, the characteristics are It will be good.

〔Example〕

FIG. 1 shows a cutaway side view of essential parts of one embodiment of the present invention, and FIG.
Symbols used in the drawings indicate the same parts or have the same meaning.

In the figure, 8 is an n-type InP gate layer, 9 is a p+ type I
Each shows an nP gate region.

Examples of main data in each part are as follows.

(11 Thickness of gate layer 8: 0.2 (μm) Impurity: S Impurity concentration: 1×10 1” (cI++, −”) Note that it may be undoped.

(2) Depth of gate region 9: 70.2 Gμm] Impurity: Zn Impurity concentration: l n-type InO, S3G a D, 4
Itail for 7A S.

When manufacturing the transistor of this example, semi-insulating In
An n-type InGaAs channel layer 2 and an n-type InP gate layer 8 are formed on a P substrate 1, Zn is diffused into the gate layer 8 to form a p+-type InP gate region 9, and the gate region 9 is used as a gate electrode 4. I am trying to do mesa etching using it as a mask.

In this case, Zn can be diffused to an appropriate depth as long as it does not invade the n-type InGaAs channel layer 2, and strict control is not required at all. The reason for this is, for example, as shown in the figure, p
Even if the n-type InP gate layer 8 remains under the +-type InP gate fiI region 9, the n-type InP gate layer 8 is depleted when this embodiment is operated.

In addition, the diffusion speed of Zn to InGaAs is
It is much slower than that for nP, so diffusion rarely becomes too deep.

In addition, the p+ type InP gate region 9 and the n''' type InP gate region 9
When mesa etching the gate layer 8, the underlying layer is n-type I.
Since it is an nGaAs channel layer 2, its mesa etching is reliably stopped at the underlying surface. Incidentally, the etchant for InP is usually HC&+H20, and
That of GaAs is H2SO4+H2O2+H20.

〔Effect of the invention〕

In the junction field effect transistor of the present invention, a low impurity concentration or undoped InP gate layer is formed on the n-type InGaAs channel layer, and Zn is diffused into the gate layer to form a p + -type InP gate layer. It has a structure in which a gate region is formed.

By adopting the above structure, strict control of Zn diffusion during manufacturing is not required, and even if the control of Zn diffusion is poor and an InP gate layer remains on the n-type InGaAs channel layer, In the operating state, the InP gate layer is depleted, so there is no problem at all, and the mesa etching of the gate layer and gate iI region can be reliably stopped at the channel layer surface, resulting in improved characteristics. will be good.

[Brief explanation of the drawing]

FIG. 1 is a cutaway side view of the main part of an embodiment of the present invention, and FIG. 2 is a cutaway side view of the main part of a conventional example. In the figure, ■ is a semi-insulating InP substrate, and 2 is an n-type 1nG substrate.
aAS channel layer, 3 is a p+ hairstyle InP layer, 4 is a gate electrode, 5 is a source electrode, 6 is a drain electrode, 7 is a gate electrode, 8 is an n-type InP gate layer, 9 is a p+ type In
Each shows a P gate region. Patent Applicant Fujitsu Ltd. Representative Patent Attorney Akira Aitani Representative Patent Attorney Hiroshi Watanabe - Cut-away side view of main parts of embodiment Cut-away side view of main parts of conventional example A--8 C〒1

Claims (1)

[Scope of Claims] A channel layer made of n-type InGaAs formed on a substrate; an InP gate layer formed on the n-type InGaAs channel layer and having a lower impurity concentration than the n-type InGaAs channel layer; and the InP gate layer. p^+ type I formed by diffusing Zn into
A junction field effect transistor comprising an nP gate region.