JPS63127557A - Chip carrier, chip mounted components and semiconductor chip mounting structure using this chip carrier - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention provides a chip carrier disposed between a semiconductor chip and a circuit board on which this semiconductor knob is mounted, and a chip carrier using the chip carrier. Related to chip mounting components and semiconductor chip mounting structures.

[Conventional technology]

Conventionally, in large computers that require high-speed calculations, the so-called matched termination method is used, in which the circuit board such as a printed board has a strip line structure to keep the characteristic impedance constant, and a resistor that matches the characteristic impedance is placed at the end of the line. There are some that carry out signal transmission. The circuit board structure of a computer that requires such high-speed performance preferably has a thin film resistive element on a ceramic multilayer circuit board, and a high-density polyimide multilayer wiring thereon. However, since advanced technology is required to perform high-density patterning on large substrates, a reduction in process yield has become a problem.

The aforementioned decrease in yield can be prevented by adopting a chip carrier structure and forming a resistor for termination matching, a wiring layer for connecting semiconductor chips, etc. on the chip carrier.

For this reason, a chip carrier structure has been employed in computers requiring high speed, as disclosed in, for example, Japanese Patent Laid-Open No. 199552/1983.

The chip carrier 01 described in the above-mentioned Japanese Patent Application Laid-Open No. 58-199552 includes a carrier substrate 01a, as shown in FIG. The carrier substrate 01a has a through hole O1b in which a conductor is accommodated, and a power supply wiring layer 01c is provided therein. A resistor O1d and a wiring 01e are formed on either the upper surface or the lower surface of the carrier substrate 01a by a thin film or thick film method, and the power supply wiring layer 01c
A through hole 01f connected to is provided. The wiring 01e connects between the through hole O1b and the resistor O1d and between the through hole O1f and the resistor O1d. Further, the resistor O1d has a highly accurate resistance value obtained by laser trimming.

A semiconductor chip 02 is mounted on the upper surface of the chip carrier 01 equipped with the components indicated by 01a to 01f through solder, and the lower surface is connected to a circuit board 03 through solder.

[Problem that the invention seeks to solve]

By the way, for computers that require high-speed calculation,
On the laser-trimmed resistor O1d, copper (Cu) with low dielectric constant and low resistance, nickel-gold alloy (Ni-Au
It is necessary to form a conductor-polyimide thin film using a conductor such as alloy). However, the heat treatment during polyimide film formation reaches a maximum temperature of 400°C.

For this reason, when the resistor O1d is a thin film resistor O1d, the resistance value changes drastically and re-trimming is required, but trimming from above the polyimide film still poses a problem in terms of reliability. In addition, when the thick film resistor is 01d,
Although it is stable when heat treated at about 400°C, it is difficult to match with the subsequent process of forming a conductor-polyimide thin film layer (for example, the unevenness is noticeable, making it difficult to achieve a high yield in forming a conductor-polyimide thin film layer). difficulties, etc.).

The present invention has been made in view of the above-mentioned circumstances, and provides a chip carrier equipped with a resistor for termination matching, which has good matching with the conductor-polyimide thin film layer forming process in the subsequent process, and is also capable of achieving good matching with the process of forming a conductor-polyimide thin film layer in the subsequent process. The main purpose of the present invention is to provide a chip carrier having a structure that can maintain the resistance value of a resistor for termination matching with high precision.

Another main object of the present invention is to provide a semiconductor chip mounting structure using the chip carrier.

[Means for solving problems]

In order to achieve the above object, a chip carrier according to the first invention of the present application includes: a chip connection surface having a plurality of chip connection terminals connected to a semiconductor chip; and a surface opposite to this chip connection surface. 4. In a chip carrier equipped with a circuit board connection surface having a plurality of circuit board connection terminals connected to a circuit board, between the chip connection surface and the circuit board connection surface, a plurality of conductors are housed inside. A carrier board having a conductor-accommodating through-hole and a plurality of resistor-accommodating through-holes in which a resistor is housed is disposed, and the plurality of chip connection terminals and the plurality of board connection terminals are connected to the conductor-accommodation through-hole. It is characterized in that it is connected via a hole or a through hole for accommodating the resistor.

Further, the chip carrier according to the second invention of the present application is characterized in that at least one of the chip connection surface and the circuit board connection surface is formed of a thin film wiring layer.

Further, a chip mounting component according to a third invention of the present application is characterized in that it is composed of the chip carrier and a semiconductor chip face-down bonded to the chip connection surface of the chip carrier.

Further, in the chip mounting component according to the fourth invention of the present application, a sealing member is disposed in the gap between the chip carrier and the surface of the semiconductor chip face-down bonded to the chip connection surface of the chip carrier. It is characterized by having been established.

Further, the semiconductor chip mounting structure according to the fifth invention of the present application is as follows:
A plurality of chip mounting components each including the chip carrier and a semiconductor chip face-down bonded to the +iii chip connection surface of the chip carrier,
It is characterized by wireless bonding to a single circuit board.

Further, the semiconductor chip mounting structure according to the sixth invention of the present application is as follows:
A semiconductor chip mounting structure in which a plurality of chip mounting components each including the chip carrier and a semiconductor chip face-down bonded to the chip connection surface of the chip carrier are wirelessly bonded to one circuit board, The present invention is characterized in that a sealing member is disposed in a gap between a peripheral edge of the circuit board connection surface of the chip carrier and a circuit board facing the peripheral edge.

Further, the semiconductor chip mounting structure according to the seventh invention of the present application is as follows:
In a semiconductor chip mounting structure in which a plurality of chip mounting components including the chip carrier and a semiconductor chip face-down positioned on the chip connection surface of the chip carrier are wirelessly bonded to a single circuit board. , a cooling plate is disposed above the back surface of the semiconductor chip, and a heat conductive member is interposed between the back surface of the semiconductor chip and the cooling plate for transmitting heat of the semiconductor chip to the cooling plate; The thermally conductive member is characterized by having thermally conductive grease.

Further, the semiconductor chip mounting structure according to the eighth invention of the present application is as follows:
A plurality of chip-mounted components each including the chip carrier and a semiconductor chip face-down bonded to the chip connection surface of the chip carrier are wirelessly bonded to a single circuit board, and In the semiconductor chip mounting structure, a cooling plate is disposed above the back surface, and a heat conductive member is interposed between the back surface of the semiconductor chip and the cooling plate for transmitting heat of the semiconductor chip to the cooling plate. A plurality of chip-mounted components are wirelessly bonded onto the circuit board by arranging leg members between the peripheral edge of the circuit board and the peripheral edge of the cooling plate to airtightly seal the space between them. It is characterized by being completely sealed.

[For production]

The chip carrier according to the first invention of the present application having the above-mentioned configuration connects the chip connection terminal to the circuit board through the resistor housing through hole of the carrier board disposed between the chip connection surface and the circuit board connection surface. The connection terminal is connected.

Therefore, by appropriately selecting the thickness of the carrier substrate, that is, the length of the resistor-accommodating through-hole, the diameter of the resistor-accommodating through-hole, and the material of the resistor housed in the resistor-accommodating through-hole, the chip The resistance value between the connection terminal and the board connection terminal can be set to an appropriate value. The surface of the carrier substrate is flat because no circuit elements such as thin film resistors or thick film resistors are formed thereon.

Therefore, when performing a thin film wiring layer forming process such as a conductor-polyimide thin film layer forming process on the chip connection surface or circuit board connection surface formed on the flat surface of the carrier substrate, a high yield of thin film wiring layer formation can be achieved. can be achieved.

Furthermore, since various materials can be used for the resistor housed in the resistor housing through-hole, the range of material selection is wider than in the conventional technique of forming a resistor on the surface of the carrier substrate using thin film formation technology. . Therefore, as the material of the resistor, a material whose resistance value does not easily change during high-temperature heat treatment in the thin film wiring layer forming process can be used. Moreover, since the resistor formed in this way is not formed on the surface of the chip carrier but inside, it is difficult to form a thin film wiring layer on the surface of the chip carrier, that is, on the chip connection surface or the circuit board connection surface. , it is becoming more and more difficult to be influenced.

Further, in the chip carrier according to the second invention of the present application, at least one of the chip connection surface and the circuit board connection surface is formed of a thin film wiring layer. The connection terminal (chip connection terminal or circuit board connection terminal) provided on the connection surface formed by this thin film wiring layer is
The positions of the terminals arranged on the surface of the thin film wiring layer can be formed to correspond to the terminal arrangement of the semiconductor chip or circuit board.

Further, the chip mounting component according to the third invention of the present application is configured as a one-chip component consisting of the chip carrier and the semiconductor chip face-down bonded to the chip connection surface of the chip carrier. It is more convenient to handle than handling the carrier separately.

Further, in the chip mounting component according to the fourth invention of the present application, in the chip mounting component integrated into one chip, the gap between the chip connection surface and the surface of the semiconductor chip face-down bonded to the chip connection surface is sealed. The structure is moisture resistant due to the arrangement of these parts. Therefore, storage, handling, etc. of chip-mounted components become easier.

Further, the semiconductor chip mounting structure according to the fifth invention of the present application is as follows:
A plurality of chip mounting components each including the chip carrier and a semiconductor chip face-down bonded to the chip connection surface of the chip carrier are wirelessly bonded to one circuit board. This eliminates the need to form a thin film wiring layer for connecting semiconductor chips on a large-area circuit board. That is, when forming a thin film wiring layer for connecting a semiconductor chip, it can be formed on a chip carrier having a relatively small area. Therefore, problems caused by warping of the patterned surface during patterning of the thin film wiring layer are eliminated. Furthermore, in the case of a semiconductor chip glue pair, the chip-mounted component may be repaired, but at this time, if there is no thin film wiring layer on the circuit board, the repair resistance of the circuit board will be improved.

Further, the semiconductor chip mounting structure according to the sixth invention of the present application is as follows:
In the semiconductor chip mounting structure in which a plurality of chip mounting components each including the chip carrier and a semiconductor chip face-down bonded to the chip connection surface of the chip carrier are wirelessly bonded to one circuit board, A sealing member is disposed in a gap between the peripheral edge of the circuit board connection surface of the chip carrier and the circuit board facing the peripheral edge. Therefore, the electrical connection between the chip carrier and the circuit board is protected by the sealing member.

Further, the semiconductor chip mounting structure according to the seventh invention of the present application is as follows:
In the semiconductor chip mounting structure in which a plurality of chip mounting components each including the chip carrier and a semiconductor chip face-down bonded to the chip connection surface of the chip carrier are wirelessly bonded to one circuit board, A cooling plate is disposed above the back surface of the semiconductor chip, and a heat conductive member is interposed between the back surface of the semiconductor chip and the cooling plate to transfer the heat of the semiconductor chip to the cooling plate. The component includes thermally conductive grease. When the heat generated in the semiconductor chip is transferred to the cooling plate through the thermally conductive grease,
It is possible to absorb deformations caused by warping of circuit boards, cooling plates, etc.

Further, the semiconductor chip mounting structure according to the eighth invention of the present application is as follows:
A plurality of chip mounting components including the chip carrier and a semiconductor chip face-down bonded to the chip connection surface of the chip gear carrier are wirelessly bonded to one circuit board, and further,
A semiconductor chip package in which a cooling plate is disposed above the back surface of the semiconductor chip, and a heat conductive member is interposed between the back surface of the semiconductor chip and the cooling plate for transmitting heat of the semiconductor chip to the cooling plate. In the structure, leg members are disposed between the peripheral edge of the circuit board and the peripheral edge of the cooling plate to airtightly seal the gap between them, so that a plurality of pieces are wirelessly bonded on the circuit board. All chip-mounted parts are sealed. In this way, a plurality of chip-mounted components wirelessly bonded onto one circuit board and the electrical connections between the chip-mounted components and the circuit board can all be sealed at once.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

In addition, in each example, corresponding components include the following 2.
Use codes with the same number of digits but different numbers of three or more digits. In the description of the nth (n≧2) embodiment,
Detailed explanations that overlap with those of the first embodiment will be omitted.

1 to 3 show a first embodiment of the present invention, FIG. 1 is a side view showing an example of a semiconductor chip mounting structure using a chip carrier according to the present invention, and FIG. FIG. 3 is a detailed explanatory diagram of the main parts of the chip carrier shown in FIGS. 1 and 2 (that is, the carrier substrate constituting the chip carrier).

The chip carrier 1 shown in FIGS. 1 and 2 includes ten carrier bases 2. The chip carrier 1 shown in FIGS. As is clear from FIG. 3, this carrier substrate 2 includes a carrier substrate upper surface 2a and a carrier substrate lower surface 2b. Between the carrier board upper surface 2a and the carrier board lower surface 2b of this carrier board 2, there are a plurality of conductor accommodation through holes 2c12C, each having a conductor therein, and a plurality of resistors each having a resistor therein. Body accommodation through holes 2d, 2d・
... is formed.

The carrier substrate 2 is made of mullite (250 μm thick) (
Approximately 450. +1
m pitch, 100 μm diameter holes with an electron beam (or
A conductor-accommodating through-hole 2c, which is opened by laser, punching, etc., and a conductor layer (W) is embedded by a mask printing method;
2e... and a resistor for impedance matching (
Resistor housing through hole 2d filled with Cr oxide
, 2d... are stacked together to form 16
It was fired at 00°C. Since this carrier substrate 2 is thick, the resistance value can be controlled by controlling this thickness. For example, after designing and manufacturing a target resistance value of 55 Ω with a thickness of 1, the target resistance value can be achieved by grinding both sides of the carrier base +7i 2 so that the average resistance value is 50 Ω. can. Note that when the mullite green sheet is punched, the accuracy of the punching is high, so that the variation in resistance value can be further reduced.

As shown in FIG. 2, the lower surface 2 of the carrier substrate
A conductor-polyimide thin film layer 3 is formed on b. This conductor-polyimide thin film layer 3 is made of polyimide resin 3a coated on the carrier substrate lower surface 2b in this embodiment.
Then, the etched part is plated with Ni-Au and C.
It is composed of a plurality of circuit board connection terminals 1a, la, . . . formed of a conductor such as U plating or Cr-Cu vapor deposition. and the circuit board connection terminal 1a,
la... is connected to either the conductor accommodating through hole 2c or the resistor accommodating through hole 2d.

Further, in this embodiment, the circuit 7. -t+ffl connection surface 1b is formed.

A conductor-polyimide thin film layer 4 is formed on the upper surface 2a of the carrier substrate. This conductor-polyimide thin film layer 4 is formed in multiple layers, and in this embodiment, the conductor-accommodating through holes 2c, 2c... on the upper surface 2a of the carrier substrate and the resistor-accommodating through holes 2d, 2d...
A plurality of carrier substrate upper surface terminals 4a, 4a... formed from a Cu thin film on the upper end surface, and a lower polyimide thin film layer 4.
b and an upper polyimide thin film layer 4c. A CLI thin film wiring layer 4d is disposed between the lower polyimide thin film layer 4b and the upper polyimide thin film layer 4b, and this Cu thin film wiring layer 4d is connected to the carrier substrate upper surface terminals 4a, 4a... It is connected to the. Further, chip connection terminals 1c, lc... formed of a thin film of Cu are formed on the upper polyimide thin film layer 4c, and these chip connection terminals 1c, lc... are formed of the thin film of Cu. Wiring layer 4d, carrier board top terminal 4a
, 4a... through the conductor-accommodating through-hole 2c,
2c... or resistor housing through hole 2d, 2d...
... is connected to the top end of the...

In this embodiment, the conductor-polyimide thin film layer 4 includes the carrier substrate upper surface terminals 4a, 4a, . . . , a lower polyimide thin film layer 4b, an upper polyimide thin film layer 4c, a Cu thin film wiring layer 4d, and a chip connection terminal 1c. , lc...
It consists of

Further, in this embodiment, the upper polyimide thin film layer 4c
A chip connection surface 1d of the chip carrier 1 is formed by the surfaces of the chip connection terminals 1c, lc, . . . .

The chip carrier 1 has the above-mentioned symbols la to 1.
It is composed of the elements shown in d and 2 to 4.

On the chip connection surface 1d, the surface (lower surface in the figure) 5a of the semiconductor chip 5 has solder bumps (for example, Pb
5XSn: Solder containing lead and 5% tin by weight) 6
．． Face-down bonding is performed via 6.... Then, the chip connection surface 1d and the semiconductor chip 5
The space between the surface 5a and the surface 5a is filled with sealing resin 7.

The sealing resin 7 is disclosed in Japanese Patent Application No. 60-27680.
It is advantageous to use a resin of the following composition as shown in No. 7.

Epicote 828 100 parts Polybutadiene (CTVN) 15 parts Dicyandiamide 10 parts Imidazole (2P4MHz) 5 parts Quartz powder (EM
C-Y2O) 55 Vo1% Resin 7 with this composition
When using the semiconductor chip 5 and the chip carrier 1
The lifespan of the solder bumps 6.6... between them has about 10 times the thermal fatigue resistance of a bare flip chip structure. Also, PCT (Pre-ssur Cook Te5t)
It has also been confirmed in tests that it has a moisture-resistant structure that can withstand 800 hours. The reason for the improved PCT resistance is the strong adhesion to the substrate, which is different from transfer mold type resins that contain a mold release agent.

A chip mounting component 8 is constituted by the components indicated by the numerals 1 to 7.

As shown in FIGS. 2 and 1, connection terminals 9a are provided on the upper surface of the circuit board 9 made of a multilayer ceramic substrate. The connection terminal 9a is composed of a tungsten (W) sintered layer 9b and a nickel (Ni) plating layer 9c. the circuit board connection terminal 1a;
la... are wirelessly bonded to the connection terminals 9a on the upper surface of the circuit board 9 via solder bumps 10, 10....

In this way, a plurality of the chip mounting parts 8°8...
* is wirelessly bonded to the upper surface of the circuit board 9.

A high thermal conductivity plate 12 is fixed to the back surface 5b (upper surface in FIG. 1) of the semiconductor chip 5 via a thermally conductive adhesive 11 such as resin or solder having good thermal conductivity. On the upper surface of this high heat conduction plate 12, comb-like protruding members 12a, 1
2a... is formed. This (teeth-like protruding member 1
2a, 12a... are the cooling plates 1 disposed above them.
3 are inserted into the recesses 13a, 13a... Thermal conductive grease 14 is filled in the recesses 13a, 13a, . . . . Therefore, the heat generated in the semiconductor chip 5 is transferred to the high heat conduction plate 12, and is transferred to the cooling plate 13 from the comb-like protruding members 12a, 1-2a, . . . via the thermal conductive grease 14. It is meant to be transmitted. The cooling plate 13 has a water passage 1
3a is formed, and cooling water is circulated through the water passage 13a. A leg portion 13b is provided on the outer peripheral portion of the lower surface of the cooling plate 13. This leg 13
The lower end of b is fixed to the outer periphery of the circuit board 9 with a sealing resin 15. Therefore, the circuit board 9
A plurality of chip mounting components 8, 8, .

Bin terminals 16 are provided on the lower surface of the circuit board 9, and a multi-chip module 17 is constructed from the components indicated by the above-mentioned numerals 1 to 16.

The pin terminals 16 of the multi-chip module 17 are inserted into through holes 18a of the multilayer printed circuit board 18. The through hole 18a is filled with solder (for example, 5n-18%B1-45%pb solder) 19, and the bin terminal 16 is fixed to the multilayer printed circuit board 18 by the solder 19. In this way, a plurality of multichip modules 17 are mounted on one multilayer printed circuit board 18.

Next, the operation of the first embodiment of the present invention having the above-described configuration will be explained.

Chip connection terminals 1c, lc of the chip carrier 1;
... and circuit board connection terminals 1a, la... are resistor-accommodating through holes 2d, 2d, etc. of the carrier board 2 disposed between the chip connection surface 1d and the circuit board connection surface 1b.
It is connected via... Therefore, the thickness of the carrier substrate 2, that is, the resistor housing through hole 2d.

2d..., the diameter of the resistor housing through-holes 2d, 2d..., and the material of the resistor accommodated in the resistor housing through-holes 2d, 2d..., as appropriate. By selecting chip connection terminals 1c, lc
... and the circuit board connection terminals 1a, la... can be set to appropriate values. Therefore, the diameter of the resistor housing through holes 2d, 2d...
By appropriately selecting the material of the resistor to be accommodated in the resistor housing through-holes 2d, 2d, etc., and later grinding the upper or lower surface of the carrier substrate 2, the thickness of the carrier substrate 2 can be adjusted. By adjusting , the chip connection terminal 1
c, lc... and circuit board connection terminals 1a, la...
・The resistance value between can be set to an appropriate value.

By forming the resistor inside the carrier substrate 2 in this way, there is no need to form a resistance element for termination matching such as a thin film resistor or a thick film resistor on the surface of the carrier substrate 2. 2 can be formed to have a flat surface.

Therefore, when forming the conductor-polyimide thin film layer 3 or 4 on the carrier substrate upper surface 2a or the carrier substrate lower surface 2b to form the chip connection surface 1d or the circuit board connection surface 1b, the carrier substrate upper surface 2a or Since the lower surface 2b of the carrier substrate is a flat surface, a high yield in forming the conductor-polyimide thin film layer 3 or 4 can be achieved. In addition, the resistor housing through hole 2
The Cr oxide used as the material for the impedance matching resistor housed in d, 2d... is disposed inside the carrier substrate 2, not on the surface of the carrier substrate 2. During the heat treatment in the process of forming the conductor-polyimide thin film wiring layer 3 on the surface of the carrier substrate 2, that is, the upper surface 2a of the carrier substrate, the resistance value is difficult to change. Therefore, the resistor housing through hole 2d of the carrier substrate 2 constituting the chip carrier 1
, 2d, . . . , the resistance values of the respective resistors formed by the resistors have little variation.

Further, the electrical connection between the chip carrier 1 and the semiconductor chip 5 by the solder bumps 6, 6, . The resin 7 protects it from moisture, dust, or external mechanical forces.

Furthermore, as described above, a Cu thin film wiring layer 4 for connecting the semiconductor chip 5 is provided on the chip connection surface ld side of the chip carrier 1.
d, there is no need to provide a wiring layer for connecting the semiconductor chip 5 on the circuit board 9. When repairing (or replacing) the semiconductor chip 5, it is sufficient to repair the chip mounting component 8, which is made up of the components indicated by the reference numerals 1 to 7. When repairing the chip mounting component 8, the Cu thin film wiring layer 4d for connecting the semiconductor chip 5 formed on the chip carrier 1 can also be repaired (or replaced) at the same time. In this way, when the wiring layer for connecting the half- and nine-chip chips 5 is not formed on the circuit board 9, when the semiconductor chip 5 is repaired, the circuit board 9
Its own repair resistance improves. Furthermore, by forming the wiring layer for connecting the semiconductor chip 5 on the relatively small area chip carrier 1 instead of forming it on the relatively large area circuit board 9, it is possible to reduce the circuit board thickness during patterning. Problems caused by warping of the circuit board 9 have been solved, and the circuit board 9
The manufacturing yield will be improved.

comb-like protruding members 12a, 12a, . . . on the upper surface of the high heat conductive plate 12 fixed to the back surface 5b of the semiconductor chip 5;
Thermal conductive grease 14 is filled between the recesses 13a, 13a, . . . of the cooling plate 13, and
2a.

12a... and the recesses 13a, 13a... and absorbs the strain caused by the difference in coefficient of thermal expansion of these members.

Further, the plurality of chip mounting components 8, 8, . , protected from dust, etc.

Further, the multi-chip module 17 is easily connected and fixed to a multilayer printed circuit board 18 through its pin terminals 16.

Next, a second embodiment of the carrier substrate will be described with reference to FIG.

The carrier substrate 102 shown in FIG. 4 has a substrate main body 2 having exactly the same structure as the carrier substrate 2 shown in FIG. After adjusting the resistance values of the holes 2d, 2d, . . . , an upper conductor-embedded mullite green sheet 2e and a lower conductor-embedded mullite green sheet 2f are superposed on the upper surface 2a and lower surface 2b of the substrate body 2. Therefore, the upper surface of the upper surface side conductor-embedded mullite green sheet 2e causes the carrier substrate upper surface 102a to
is formed, and the lower surface of the lower surface side conductor-embedded mullite green sheet 2f forms the carrier substrate lower surface 102b.

The upper surface side conductor-embedded mullite green sheet 2e and the lower surface side conductor-embedded mullite green sheet) 2f have conductor accommodation through holes 2g, 2g in which conductors are embedded.
...is provided. The conductor-accommodating through-holes 2e, 2e, . Accommodation through hole 2
d, 2d... are connected.

It is also possible to reduce the thickness of the resistor-accommodating through-holes 2d, 2d, . . . and make the conductor layers on the upper and lower surfaces thicker than the thickness of the resistor-accommodating through-holes by selecting the resistor.

In this way, by arranging the upper surface side conductor-embedded mullite green sheet 2f and the lower surface side conductor-embedded mullite green sheet 2g, the carrier substrate upper surface 102a of the carrier substrate 102 and the carrier substrate lower surface 102
When forming chip connection terminals or circuit board connection terminals on b, uniform adhesion strength of each terminal is ensured.

Next, a third embodiment of the carrier substrate will be described with reference to FIG.

The carrier substrate 202 shown in FIG. 5 includes a carrier substrate upper surface 202a and a carrier substrate lower surface 202b. The carrier substrate upper surface 2 of this carrier substrate 202
02a and the lower surface 202b of the carrier board are a plurality of conductor accommodating through holes 202c in which conductors are accommodated.
, 202c... and a plurality of resistor-accommodating through-holes 202d, 202d, in which resistors are housed.
... is provided.

The carrier substrate 202 is formed from three mullite (SiO□Ah(h) green sheets with a thickness of 250 μm.
A through hole with a 0 μm pinch and a diameter of 100 μm is made using an electron beam (or saber, punching, etc.). Then, the conductor-accommodating through-holes 202c, 202c... are formed by embedding a conductor layer (W) in the through-hole by a mask printing method, and a resistor (Cr oxide) for impedance matching is formed. By embedding, the resistor housing through holes 202d, 202d, . . . are formed. Three such mullite green sheets are stacked on top of each other with the positions of the conductor housing through holes 202c, 202c... and the resistor housing through holes 202d, 202d... shifted, and fired at 1600°C to form the carrier. A substrate 202 is formed. In this way, by shifting the positions of the mullite green sheets and overlapping them, the resistor housing through holes 202d, 202 are formed.
It is possible to adjust the resistance value of d.... Furthermore, since the carrier substrate 202 is thick, the resistance value can also be controlled by controlling the thickness. Note that the resistor housing through holes 202d, 2
As the resistor to be embedded in 02d..., it is also possible to use a paste containing a resistor made of an alloy of W, glass, Fe, Ni, Mn, Cu, etc. in addition to the Cr oxide. Moreover, it is also possible to use a glass ceramic substrate instead of the mullite green sheet, and in that case, a glass-ceramic substrate mixed with Ag-Pd as the conductor and ruthenium oxide (R20) or 8g-Pd as the resistive layer can be used. You can use things like

Next, a fourth embodiment of the carrier substrate will be described with reference to FIG.

The carrier substrate 302 shown in FIG. 6 includes a carrier substrate upper surface 302a and a carrier substrate lower surface 302b. The carrier substrate upper surface 3 of this carrier substrate 302
02a and the lower surface 302b of the carrier board are a plurality of conductor-accommodating through-holes 302c in which conductors are accommodated.
, 302c... and a plurality of resistor housing through-holes 302d, 302d.
... is formed.

The conductor accommodating through holes 302c, 302c, . . . are filled with a suitable conductor 302e such as Cu paste.

The resistor housing through holes 302d, 302d...
is formed by inserting a resistance wire 302f into the through hole, embedding Cu paste 302g, etc. on both sides of the through hole, and then irradiating both ends of the through hole with a laser L. By irradiating both ends of the resistor housing through-holes 302d, 302d... with the laser L, the resistance value is reduced, so by adjusting the irradiation amount of the laser I7,
The resistance values of d, 302d, . . . can be controlled. Rhenium (19
, 2μΩcm), lanthanum (57μΩcIfl), Zr
(40μΩc!11), copper nickel (49μΩcffl
), manganin (39 μΩcna), etc., it is possible to control the resistance value of the resistor housing through holes 302d, 302d, . . . to about 50Ω.

Next, a fifth embodiment of the carrier substrate will be described with reference to FIG. FIG. 7(A) shows the carrier substrate 40 of the fifth embodiment.
2, and FIG. 7(b) is an explanatory diagram of the manufacturing method thereof.

The carrier substrate 402 shown in FIG. 7(a) includes a carrier substrate upper surface 402a and a carrier substrate lower surface 402b. Between the carrier substrate upper surface 402a and the carrier substrate lower surface 402b of this carrier substrate 402,
A plurality of conductor-accommodating through-holes 4 in which conductors are housed
02c, 402c... and a plurality of resistor housing through holes 402d, 402d in which resistors are housed.
... is formed.

The conductor accommodating through holes 402c, 402c...
is formed of a suitable conductor 402e such as Cu inserted into the through hole and an epoxy resin 402f filled around the conductor 402e. The resistor housing through holes 402d, 402d, . . . are formed by a suitable resistance wire 402g inserted into the through hole and an epoxy resin 402h filled around the resistance wire 402g.

Next, a method for manufacturing the carrier substrate 402 having the above-described configuration will be explained with reference to FIG. 7(b).

A large number of large substrates with through holes of 150μ in diameter are stacked with mold release agent 4021 in between, and the holding frame K
Positioning is done by After passing a copper wire 402e or resistance wire 402g with a diameter of 100μ through the through hole, a heat-resistant, adhesive, and fluid resin (for example, epoxy resin) is applied to the gap between the through holes on the lower board side. Aspirate and fill.

After this resin is cured, the large substrates are separated and cut using a wire saw or the like, and then both surfaces are ground to adjust the resistance value. The separated substrates are cut into individual carrier substrates 402. Then, the carrier substrate upper surface 402a and the carrier substrate lower surface 402b of the carrier substrate 402 are polished.

Next, a second embodiment of a circuit board connection surface and a chip connection surface of a chip carrier, and a bonding structure between these connection surfaces, a circuit board, and a semiconductor chip will be described with reference to FIG. The carrier substrate of the chip carrier 101 shown in FIG. 8 is formed exactly the same as the carrier substrate 2 shown in FIG. 2.

A conductor-polyimide thin film layer 103 is provided on the lower surface 2b of the carrier substrate 2 constituting the chip carrier 101.
is formed. This conductor-polyimide thin film layer 103 is
In this embodiment, the polyimide resin 103a coated on the lower surface 2b of the carrier substrate, and the etched portion of the polyimide resin 103a are coated with Ni-Au plating, Cu plating or Cr-C.
It is composed of a plurality of circuit board connection terminals 101a, 101a, . . . formed of a conductor such as U vapor deposited.

And the circuit board connection terminals 101a, 101a.
... is connected to either the conductor housing through hole 2C or the resistor housing through hole 2d. Also,
In this embodiment, a circuit board connection surface 101b of the chip carrier 101 is formed by the surface of the polyimide resin 103a and the surfaces of the circuit board connection terminals 101a, 101a, . . . .

A conductor-polyimide thin film layer 104 is formed on the upper surface 2a of the carrier substrate. This conductor-polyimide thin film layer 104 is formed in multiple layers, and in this embodiment, the conductor-accommodating through holes 2c, 2c,
...Top end surface and resistor housing through holes 2d, 2d.
. . . a plurality of carrier substrate upper surface terminals 104a, 104a, . . . formed from a Cu thin film on the upper end surface; a lower polyimide thin film layer 104b;
and an upper polyimide thin film layer 104d.

A lower thin film wiring layer 104e made of Cu is disposed between the lower polyimide thin film layer 104b and the intermediate polyimide thin film layer 1040, and the intermediate polyimide thin film layer 104c and the upper polyimide thin film layer 104d
An upper thin film wiring layer 104f made of Cu is provided between them. The upper thin film wiring layer 104'' is connected to the carrier substrate upper surface terminals 104a, 104a, .
A chip connection terminal 101c formed of a thin film of
101C... are formed, and this chip connection terminal 101c.

101c... is the upper thin film wiring layer 104f of Cu.
, are connected to the conductor-accommodating through-holes 2c, 2C... or the resistor-accommodating through-holes 2d, 2d... via the lower thin film wiring layer 104e and the carrier board upper surface terminals 104a, 104a... . And the chip connection terminal 101c.

As is clear from FIG. 8, the intervals of 101c...
The carrier board upper surface terminals 104a, 104a...
The spacing is smaller than the spacing between the two. These are the chip connection terminals 101c and 101c of the chip carrier 101.
This is to match the spacing between the terminals of the semiconductor chip 105, which will be described later.

In this embodiment, the conductor-polyimide thin film layer 104 includes the carrier substrate top terminals 104a, 104a...
, a lower polyimide thin film layer 104b, an intermediate polyimide thin film layer 104c, an upper polyimide thin film layer 104d, a lower thin film wiring layer 104e, an upper thin film wiring layer 104f, and chip connection terminals 101c, 101c...

Further, in this embodiment, the upper polyimide thin film layer 10
4d surface and chip connection terminals 101c, 101c...
A chip connection surface 101d of the chip carrier 101 is formed by the surface of the chip carrier 101.

The chip carrier 101 includes the aforementioned reference numeral 10.
It is composed of elements shown as 1a to 101d, 2 and 103 to 104.

A chip surface thin film wiring layer 105C and chip surface terminals 105d, 105d, . .

And the connection terminal 101c of the chip carrier 101
.

101c... have chip surface terminals 105d, 10
5d... is a solder hump (for example, Pb-5χSn
: Solder containing lead and 5% tin by weight) 106.10
Face-down bonding is performed via 6.... The space between the chip connection surface 101d and the surface 05a of the semiconductor chip 105 is filled with a sealing resin 107.

A chip mounting component 108 is constituted by the components indicated by the reference numerals 101 and 105 to 107.

A connection terminal 109a made of a nickel (Ni) plating layer is provided on the upper surface of the circuit board 109 made of a multilayer ceramic substrate. The circuit board connection terminals 101a, 101a, . . . are wirelessly bonded to the connection terminals 109a on the upper surface of the circuit board 109 via solder bumps 110, 110, .
In this way, a plurality of the chip mounting parts 108.
108 are wirelessly bonded to the upper surface of the circuit board 9.

Next, a third embodiment of a circuit board connection surface and a chip connection surface of a chip carrier, and a bonding structure between these connection surfaces, a circuit board, and a semiconductor chip will be described with reference to FIG. It is assumed that the carrier substrate of the chip carrier 201 shown in FIG. 9 is formed exactly the same as the carrier substrate 2 shown in FIG. 2.

The carrier substrate 2 includes a carrier substrate upper surface 2a and a carrier substrate lower surface 2b. The lower surface 2b of the carrier board has a plurality of circuit board connection terminals 201a, 201a, . . . connected to the lower ends of the conductor accommodating through holes 2c, 2c, .
・is formed. Then, the lower surface 2 of the carrier substrate
b and the lower surface of the circuit board connection terminals 201a, 201a..., the circuit board connection surface 201 of the chip carrier 1.
b is formed.

A conductor-polyimide thin film layer 204 is formed on the upper surface 2a of the carrier substrate. In this embodiment, the conductor-polyimide thin film layer 204 is made of a polyimide resin 204a coated on the upper surface 2a of the carrier substrate, and a conductor such as Ni-Au plating, Cu plating, or Cr-Cu vapor deposition on the etched portion of the polyimide resin 204a. It is composed of a plurality of chip connection terminals 201c, 201c, . . . formed therein. And the chip connection terminal 201c.

201c... are connected to either the conductor accommodating through hole 2C or the resistor accommodating through hole 2d. Furthermore, in this embodiment, the polyimide resin 204
A chip connection surface 201d of the chip carrier 201 is formed by the surfaces of the chip connection terminals 201c, 201c, . . . .

The chip carrier 201 has the above-mentioned symbols 201a to 201a.
It is composed of elements indicated by 01d, 2 and 204.

On the chip connection surface 201d, the front surface (lower surface in the figure) 205a of the semiconductor chip 205 has a solder hump (Pb
-5χSn: solder containing lead and 5% tin by weight) 2
Face-down bonding is performed via 06.206... The space between the chip connection surface 201d and the surface 205a of the semiconductor chip 205 is filled with a sealing resin 207.

A chip mounting component 208 is constituted by the components indicated by the reference numerals 201 and 205 to 207.

Connection terminals 209a made of a nickel (Ni) plating layer are provided on the upper surface of the circuit board 209 made of a multilayer ceramic substrate. The circuit board connection terminals 201a, 201a... are solder bumps 210°2.
10... are wirelessly bonded to the connection terminal 209a on the upper surface of the circuit board 209. In this way, the plurality of chip mounting components 208, 20
8 are wirelessly bonded to the upper surface of the circuit board 209.

Next, a fourth embodiment of a circuit board connection surface and a chip connection surface of a chip carrier, and a bonding structure between these connection surfaces, a circuit board, and a semiconductor chip will be described with reference to FIG. Note that the carrier substrate of the chip carrier 301 shown in FIG. 10 is the same as the carrier substrate 10 shown in FIG.
2 and all (formed identically.

On the carrier substrate lower surface 102b of the carrier substrate 102,
A plurality of circuit board connection terminals 3 formed of a conductor such as Ni-Au plating, Cu plating, or Cr-Cu vapor deposition.
01a.

301a... are formed. The circuit board connection terminals 301a, 301a... are connected to the conductor accommodation through holes 2C92C... or the resistor accommodation through holes 2d via the conductor accommodation through holes 2g, 2g.
, 2d... are connected to the lower ends. Further, in this embodiment, a circuit board connection surface 301b of the chip carrier 301 is formed by the carrier board lower surface 102b and the surfaces of the circuit board connection terminals 301a, 301a, . . . .

A conductor-polyimide thin film layer 304 is formed on the carrier substrate top surface 102a. This conductor-polyimide thin film layer 304 is formed in multiple layers, and in this embodiment, a plurality of conductor-accommodating through holes 2g, 2g, . It includes terminals 304a, 304a, . . . , a lower polyimide thin film layer 304b, and an upper polyimide thin film layer 304c. These lower polyimide thin film layer 304b and upper polyimide thin film layer 304c
A Cu thin film wiring WA layer 304d is disposed between them, and this Cu thin film wiring layer 304d is connected to the carrier substrate upper surface terminals 304a, 304a, . . . . Further, on the upper polyimide thin film layer 304c, Ni-
Chip connection terminal 301c formed of a thin Au film
, 301c, .
a... and the conductor accommodating through hole 2g, 2
The conductor-accommodating through holes 2c, 2c...
Alternatively, it is connected to the upper end of the resistor housing through holes 2d, 2d, . . . .

In this embodiment, the conductor-polyimide thin film layer 304 includes the carrier substrate top terminals 304a, 304a...
, lower polyimide thin film layer 304b, upper polyimide thin film layer 304c, Cu thin film wiring layer 304d, and Ni-
It consists of 8U chip connection terminals 301c, 301c...

Further, in this embodiment, the upper polyimide thin film layer 30
4c surface and chip connection terminals 301c, 301c...
A chip connection surface 301d of the chip carrier 301 is formed by the surface of the chip carrier 301.

The chip carrier 301 includes the aforementioned reference numeral 30.
It is composed of elements shown as 1a to 301d, 102, and 304.

On the chip connection surface 301d, the surface (bottom surface in the figure) 305a of the semiconductor chip 305 is connected to solder bumps (for example, Pb-5χSn: solder containing lead and 5% tin by weight) 306, 306, etc. It is face down bonded. Then, the chip connection surface 3
The space between 01d and the surface 305a of the semiconductor chip 305 is filled with a sealing resin 307.

A chip mounting component 308 is constituted by the components indicated by the reference numerals 301 and 305 to 307.

In addition, a circuit board 3 made of a multilayer ceramic substrate
A connecting terminal 309a made of a nickel (Ni) plating layer is provided on the upper surface of the terminal 09.

The circuit board connection terminals 301a, 301a... are connected to the circuit board 3 via solder bumps 310, 310...
It is wirelessly bonded to the connection terminal 309a on the top surface of 09.

In this way, a plurality of the chip mounting components 308.3
08... are wirelessly bonded to the upper surface of the circuit board 309.

Next, a second embodiment of a mounting structure for a chip mounting component using a chip carrier according to the present invention will be described with reference to FIG.

The chip mounting component 8 in the second embodiment of this mounting structure has exactly the same structure as the chip mounting component 8 shown in FIG. 1 above. Therefore, this chip mounting component 8 includes a semiconductor chip 5 face-down bonded to a chip carrier l and this chip connection surface 1d.

The mounting structure is also similar to the mounting structure shown in FIG. 1 in that a plurality of chip mounting components 8, 8, . . . are wirelessly bonded to the upper surface of the circuit board 9.

A cooling plate 113 is disposed above the back surface 5b (upper surface in FIG. 1) of the semiconductor chip 5. A passageway 113a is formed in the cooling plate 113, and cooling water circulates through the passageway 113a. The lower surface of the cooling plate 113 and the back surface 5 of the semiconductor chip 5
A thermally conductive grease 114 is filled between the Therefore, the heat generated in the semiconductor chip 5 is transferred to the cooling plate 113 through the thermally conductive grease 114.
It is intended to be transmitted to Leg members 113b are provided on the outer periphery of the lower surface of the cooling plate 113. The lower end of this leg member 113b is fixed to the outer periphery of the circuit board 9 with a sealing resin 115. therefore,
A plurality of chip mounting components 8,8, .

The cooling plate 113, leg members 113b, and resin 115 are tightened by a member 20 for mechanical strength reinforcement.

A bin terminal 116 is provided on the bottom surface of the circuit board 9, and this bin terminal 116 is a multilayer printed a'rF
It is inserted into the through hole 118a of L11B.

Solder (for example, 5n) is placed inside the through hole 118a.
-18%B1-45%PB solder) 119 is filled, and the bin terminal 116 is fixed to the multilayer printed circuit board 118 by this solder 119.

Next, a third embodiment of a mounting structure for a chip-mounted component using a chip carrier according to the present invention will be described with reference to FIG.

The chip mounting component 8 in the third embodiment of this mounting structure has exactly the same structure as the chip mounting component 8 shown in FIG. 1 above. Therefore, this chip mounting component 8 includes the semiconductor chip 5 face-down bonded to the chip carrier 1 and this chip connectable part 1d.

The mounting structure is also similar to the mounting structure shown in FIG. 1 in that a plurality of chip mounting components 8, 8, . . . are wirelessly bonded to the upper surface of the circuit board 9.

However, there is a solder sealing part 21 between the outer peripheral part of the lower surface of the chip carrier 1 of the chip mounting component 8 and the upper surface of the circuit board 9.
They are different in that they have been set up. This solder sealing part 21
By arranging the chip carrier and the circuit board 9
The moisture resistance of the electrical connections between the Therefore, in this case, there is no need to seal the entire module, so as described later, the entire module is not sealed.

A cooling plate 213 is disposed above the back surface 5b (upper surface in FIG. 1) of the semiconductor chip 5. A water passage (not shown) is formed in this cooling plate 213, and cooling water is circulated through the water passage. Thermal conductive grease 214 is filled between the lower surface of the cooling plate 213 and the back surface 5b of the semiconductor chip 5. Therefore, the heat generated in the semiconductor chip 5 is transferred to the cooling plate 213 via the thermally conductive grease 214. The outer periphery of the cooling plate 213 and the outer periphery of the circuit board 9 are connected to a plurality of connecting members 22 (1
(Only shown in the figure) are maintained at predetermined intervals. Therefore, in this case, unlike the mounting structure shown in FIG. 1 or FIG. 11, the space between the outer peripheral member of the upper surface of the circuit board 9 and the lower surface of the cooling plate 213 is not sealed. That is,
The entire module is not sealed.

By leaving the entire module open in this manner, the chip mounting component 8 can be easily removed at the time of repair.

On the bottom surface of the circuit board 9 are pin terminals 216, 216...
・ is provided, and this pin terminal 216.216...
・ is the socket 23a of the connector 23, 23a...
・It is inserted into. The pin terminals 23b, 23b, . . . of the connector 23 are inserted into the through holes 218a of the multilayer printed circuit board 218. Solder (for example, 5n-18% B1) is placed inside the through hole 218a.
-45% PB solder) 219 is filled, and with this solder 219, the pin terminals 23b, 23b...
It is fixed to the multilayer printed circuit board 218.

Next, with reference to FIG. 13, an example of a modification of the cooling structure of the semiconductor chip 5 in the mounting structure of the chip mounting component 8 using the chip carrier according to the present invention will be described.

First, a first modification of the semiconductor chip cooling structure will be described with reference to FIG. 13(a).

A cooling plate 313 is disposed above the back surface 5b (upper surface in the figure) of the semiconductor chip 5. This cooling plate 31
3 is formed with a water passage 313a, through which cooling water flows in the direction indicated by the arrow. The cooling plate 313 is provided with a thermally conductive grease storage portion 313b and a communication path 313C. The communication path 313c connects the lower surface of the cooling plate 313 and the semiconductor chip 5.
The space between the back surface 5b and the thermally conductive grease accommodating portion 313b are communicated with each other. Thermal conductive grease 314 is accommodated in the thermally conductive grease accommodating portion 313b and the communication path 313C. Further, thermally conductive grease 314 is also filled between the lower surface of the cooling plate 313 and the back surface 5b of the semiconductor chip 5. Therefore, the heat generated in the semiconductor chip 5 is transferred to the cooling plate 313 via the thermally conductive grease 314.

By employing such a configuration, dimensional changes such as expansion or contraction due to temperature changes of the cooling structure components are absorbed by the thermally conductive grease 314.

Next, a second modification of the semiconductor chip cooling structure will be described with reference to FIG. 13(b).

A thermally conductive adhesive 411 such as resin or solder with good thermal conductivity is applied to the back surface 5b (upper surface in the figure) of the semiconductor chip 5.
A high thermal conductivity plate 412 is fixed via the. This high heat conductive plate 412 is made of a high heat conductive material such as SiC, AIN, BN, etc. Further, the area of the high thermal conductivity plate 412 is larger than the area of the back surface 5b of the semiconductor chip 5. A cooling plate 413 is disposed above the high thermal conductivity plate 412. A passageway 413a is formed in this cooling plate 413, and cooling water flows in the direction indicated by the arrow in the passageway 413a. A space between the lower surface of the cooling plate 413 and the upper surface of the high thermal conductive plate 412 is filled with thermally conductive grease 414.
is filled. Therefore, the heat generated in the semiconductor chip 5 is transferred to the cooling plate 413 via the thermally conductive adhesive 411, the high thermally conductive plate 412, and the thermally conductive grease 414.

In this way, by employing the high thermal conductivity plate 412 having a larger area than the back surface 5b of the semiconductor chip 5, cooling efficiency is increased.

Next, a third modification of the semiconductor chip cooling structure will be described with reference to FIG. 13(c).

A high thermal conductivity plate 512 is disposed above the back surface 5b (upper surface in the figure) of the semiconductor chip 5 with a slight gap therebetween. The gap is filled with thermally conductive grease 514. The area of the high thermal conductivity plate 512 is larger than the area of the back surface 5h of the semiconductor chip 5. The upper surface of this high heat conduction plate 512 has comb-like protrusions 5.
12a, 512a, . . . are formed. A cooling plate 513 is disposed above the high thermal conductivity plate 512. A passageway 513a is formed in the cooling plate 513, and cooling water flows in the direction indicated by the arrow in the passageway 513a.

On the lower surface of the cooling plate 513, the comb-like protruding member 5 is provided.
12a, 512a.'' Corresponding to the recesses 513b, 51
3b-- is formed. The comb-like protruding members 512a, 512a, . . . are recessed portions 513b of the cooling plate 513 disposed above them.

513b... is inserted. This recess 513b,
513b... is filled with thermally conductive grease 514.

Therefore, the heat generated in the semiconductor chip 5 is transmitted to the high heat conduction plate 512 via the heat conduction grease 514, and the comb-like protruding members 512a, 512a...
The heat is transmitted to the cooling plate 513 via the heat conductive grease 514 in the recesses 513b, 513b, . . . .

In this way, the comb tooth-like protruding members 512a, 512a...
By adopting a structure in which the . . . are inserted into the recesses 513b, 5L3b, .

Next, a fourth modification of the semiconductor chip cooling structure will be described with reference to FIG. 13(d).

On the back surface 5b (top surface in the figure) of the semiconductor chip 5,
Thermal conductive adhesive 61 such as resin or solder with good thermal conductivity
1, a lower high heat conductive plate 612° is fixed. The area of the lower high thermal conductivity plate 612' is larger than the area of the back surface 5b of the semiconductor chip 5. m
? An upper high heat conduction plate 612 is disposed above the upper and lower high heat conduction plates 612 with a slight gap therebetween. The gap is filled with thermally conductive grease 614. The area of this upper high heat conduction plate 612 is formed to be the same as the area of the lower high heat conduction plate 612°. The upper surface of the upper high heat conduction plate 612 includes a tooth-shaped protrusion 612a,
612a... are formed. A cooling plate 613 is disposed above the upper high heat conduction plate 612. A passageway 613a is formed in this cooling plate 613, and cooling water flows in the direction of arrow A through the passageway 613a. On the lower surface of the cooling plate 613, recesses 613b, 613b, . The comb-like protruding members 612a, 612a... are recessed portions 613b, 6 of the cooling plate 613 disposed above them.
13b... is inserted. These recesses 613b, 6
13b... is filled with thermally conductive grease 614.

Therefore, the heat generated in the semiconductor chip 5 is transferred to the lower high heat conduction plate 612', the heat conduction grease 614, and the upper high heat conduction plate 612, and the comb-like protruding member 612'
a, 612a- to the recesses 613b, 613b...
・The cooling plate 6 is connected to the cooling plate 6 through the thermally conductive grease 614 inside.
13.

Next, a fifth modification of the semiconductor chip cooling structure will be described with reference to FIG. 13(e).

The chip mounting component 8'' in this modified example of the semiconductor chip cooling structure has a sealing resin 717 that is filled between the semiconductor chip 5 and the chip carrier 1.
Even the sides are sealed.

Then, a thermally conductive adhesive 711 such as a resin with good thermal conductivity or solder is applied to the back surface 5b (upper surface in the figure) of the semiconductor chip 5 and the upper surface of the sealing resin 717, so that the lower side is heated to a high temperature. A conductive plate 712' is fixed. The area of this lower high thermal conductivity plate 712' is larger than the area of the back surface 5b of the semiconductor chip 5. An upper high heat conduction plate 712 is disposed above the lower high heat conduction plate 712' with a slight gap therebetween. In the gap,
It is filled with thermally conductive grease 714. The area of this upper high heat conduction plate 712 is formed to be the same as the area of the lower high heat conduction plate 712''.
2 have comb tooth-like protrusions 712a, 712a...
・is formed.

A cooling plate 713 is disposed above the high thermal conductivity plate 712. A passageway 713a is formed in this cooling plate 713, and cooling water flows in the six directions of arrows in the passageway 713a. The cooling plate 713
The comb tooth-like protruding member 712a is provided on the lower surface of the .

Corresponding to 712a..., recesses 713b, 713b...
・is formed. the comb-like protruding member 712a;
712a... are inserted into recesses 713b, 713b... of the cooling plate 713 disposed above it. Thermal conductive grease 7 is inside these recesses 713b, 713b...
14 is filled. In addition, the upper high heat conduction plate 71
2 has a plurality of through holes 712b formed therein, and these through holes 712b are also filled with thermally conductive grease 7*4. Thermal conductive grease 7 is filled in the gap between the lower high heat conductive plate 712' and the upper high heat conductive plate 712.
14 and the recessed portion 713b.

Thermal conductive grease 714 filled in 713b communicates with the through hole 712b.

The cooling plate 713 also includes a thermally conductive grease storage portion 7.
13c and a communication path 713d are provided. The communication path 713d is connected to the recesses 713b and 713 of the cooling plate 713.
It communicates with the thermally conductive grease 714 in b...

Therefore, the heat generated in the semiconductor chip 5 is transferred to the lower high heat conduction plate 712', the heat conduction grease 714, and the upper high heat conduction plate 712, and the comb-like protruding member 712'
a, 712a- to the recessed portions 713b, 713b-.
- The cooling plate 7 via the thermally conductive grease 714 inside.
13.

Next, with reference to FIG. 14, a modified example of a chip mounting component configured by mounting a semiconductor chip on a chip carrier according to the present invention will be described.

The chip carrier 1 and semiconductor chip 5 shown in FIG. 14(A) are each constructed similarly to that shown in FIG. 1. And the semiconductor chip 5 is the chip carrier 1
is face-down bonded to the chip connection surface 1d of the semiconductor chip 5 through solder bumps 6, 6, and a sealing resin 7 is bonded between the surface (lower surface in the figure) 5a of the semiconductor chip 5 and the chip connection surface 1d. is filled. These structures are similar to those shown in FIG. The circuit board connection surface 1b of the chip carrier 1 is wirelessly bonded to the upper surface of a polyimide substrate 24 having approximately the same size as the chip carrier 1 using solder humps 110, 110, . . . . The circuit board connection terminals 1a, la... of the chip carrier 1 are connected to the solder bumps 110.1.
Terminal 2 on the upper surface side of the polyimide substrate 24 via 10...
4a, 24a... A resin 25 is filled between the circuit board connection surface 1b of the chip carrier 1 and the upper surface of the polyimide substrate 24 for sealing the electrical connections provided therebetween. The upper surface terminal 2 is provided on the lower surface of the polyimide substrate 24.
Pin terminals 24b, 24 connected to 4at24a...
b... is provided protrudingly. Said code 5 to 7.24.2
The components indicated by 5 and 110 constitute a chip mounting component 81 in this modification.

The chip mounting component 82 shown in FIG. 14(b) is constructed almost the same as the chip mounting component 81 shown in FIG.
The difference is that c is formed.

This sealing resin filling hole 24c allows the chip carrier 1
This makes it easier to fill the sealing resin 25 between the circuit board connection surface and the upper surface of the polyimide substrate 24.

Both of the chip mounting components 81 and 82 described above are configured as one-chip components.

The pin terminals 24b, 24b, . . . allow easy attachment and detachment to a large-area circuit board (not shown).

The chip carrier 1 and semiconductor chip 5 shown in FIG. 14(c) are constructed in the same way as shown in FIG. 1. The semiconductor chip 5 is face-down bonded to the chip connection surface 1d of the chip carrier 1 via solder bumps 6, 6, etc., and these structures are similar to those shown in FIG. . However, the surface (bottom surface in the figure) 5a of the semiconductor chip 5 and the chip connection surface 1
The difference is that a sealing resin is not filled between d and d. The cap 26 that covers the periphery of the semiconductor chip 5 is composed of a top portion 26a and side portions 26b. Said top part 2
6a inner surface and the back surface (in the figure, top surface) 5 of the semiconductor chip 5
b is bonded with an alloy (for example, Au-20%Sn) 27, and a sealant such as glass, solder, or resin is used between the lower end of the side portion 26b and the outer periphery of the chip connection surface 1d of the chip carrier 1. It is sealed by 28. The chip mounting component 83 in this modified example is constituted by the components indicated by the aforementioned reference numerals 1.5.6 and 26 to 28.

The chip mounting component 84 shown in FIG. 14(d) is constructed almost the same as the chip mounting component 83 shown in FIG. 14(c), except that the solder bumps 6.6. The difference is that the front surface 5a of the semiconductor chip 5 is wire-bonded to the chip connection surface 1d of the chip carrier 1 using wires 106, 106, .

Although the embodiments and modifications of the mounting structure of the present invention have been described above in detail, the present invention is not limited to the embodiments or modifications described above, and does not deviate from the scope of the invention as set forth in the claims. It is possible to make various minor changes without having to do so.

For example, when the chip carrier is constructed from a multilayer carrier substrate as shown in FIG. 3, it is also possible to form a wiring layer between the layers in the carrier substrate.

〔Effect of the invention〕

According to the above-mentioned chip carrier of the first invention of the present application, a carrier board is disposed between the chip connection surface and the circuit board connection surface of the chip carrier, and a resistor for termination matching is installed in the through hole inside the carrier board. Since the carrier substrate is housed inside, the surface of the carrier substrate can be formed flat. Therefore, the yield is improved when forming a thin film wiring layer, such as a conductor-polyimide thin film layer, on the surface of the carrier substrate to obtain a desired chip connection surface or circuit board connection surface.

In addition, various materials can be used for the resistor for termination matching, and since the resistor is housed inside the through hole of the chip carrier, the resistance value can be changed even by the high temperature heat treatment in the thin film wiring layer forming process. It is easy to prevent fluctuations and dispersion from occurring.

Further, according to the chip carrier of the second invention of the present application, the positions of the connection terminals on the thin film wiring layer forming the connection surface with the semiconductor chip or circuit board are made to correspond to the terminal arrangement state of the semiconductor chip or the circuit board. be able to. Therefore, the chip carrier of the present invention can be used for semiconductor chips or circuit boards having various terminal arrangement states.

Further, in the chip mounting component according to the third aspect of the present invention, the semiconductor chip and the chip carrier are integrated into one chip, making it convenient to handle, so that the work efficiency in the mounting process is improved.

Further, in the chip mounting component according to the fourth invention of the present application, the semiconductor chip and the chip carrier are integrated into one chip and have a moisture-resistant structure, so handling in the mounting process is extremely convenient. Therefore, the work efficiency in the mounting process is improved accordingly.

Further, the semiconductor chip mounting structure according to the fifth invention of the present application is as follows:
Since it is not necessary to form a thin film wiring layer for connecting a semiconductor chip on the circuit board, the repair resistance of the circuit board can be improved when chip-mounted parts are glued and carried.

Further, the semiconductor chip mounting structure according to the sixth invention of the present application is as follows:
The electrical connection between the chip carrier and the circuit board is sealed by the sealing member disposed in the gap between the peripheral edge of the circuit board connection surface of the chip carrier and the circuit board facing the peripheral edge. protected by the member. Therefore, the service life of the chip-mounted component can be extended.

Further, the semiconductor chip mounting structure according to the seventh invention of the present application is as follows:
Since the heat generated in the semiconductor chip is conducted from the back side of the semiconductor chip to the cooling plate through the thermally conductive grease, the heat generated by the semiconductor chip is absorbed by the deformation of the thermally conductive grease due to warping of the circuit board, cooling plate, etc. be able to.

Further, the semiconductor chip mounting structure according to the eighth invention of the present application is as follows:
Using the cooling plate, a plurality of chip-mounted components on the circuit board and the electrical connections between the chip-mounted components and the circuit board can all be sealed at once. In this way, by using the cooling plate, which is originally provided as a necessary component, the chip-mounted components and the electrical connections between the chip-mounted components and the circuit board can be connected efficiently in terms of space and man-hours. Can be sealed.

[Brief explanation of the drawing]

1 to 3 show a first embodiment of the present invention, FIG. 1 is a side view showing an example of a mounting structure of a semiconductor chip using a chip carrier according to the present invention, and FIG. 1 is an enlarged view of the main parts of FIG. 1, FIG. 3 is a detailed explanatory diagram of the main parts of the chip carrier (i.e., the carrier substrate) shown in FIGS. FIG. 5 is an explanatory diagram of the third embodiment of the carrier board, FIG. 6 is an explanatory diagram of the fourth embodiment of the carrier board, and FIG. 7(A) is an explanatory diagram of the fourth embodiment of the carrier board. FIG. 7(B) is an explanatory diagram of the method for manufacturing the carrier substrate of the fifth embodiment. FIG. 8 is a second embodiment of the portion corresponding to the configuration shown in FIG. 2. 9 is an explanatory diagram of the third embodiment of the part corresponding to the configuration shown in FIG. 2, and FIG. 10 is an explanatory diagram of the fourth embodiment of the part corresponding to the configuration shown in FIG. 2. FIG. 11 is an explanatory diagram of a second embodiment of the part corresponding to the mounting structure of a chip mounting component using the chip carrier according to the present invention shown in FIG. 1, and FIG. 12 is an explanatory diagram of the second embodiment. FIG. 13 is an explanatory diagram of a third embodiment of a portion corresponding to the mounting structure of a chip-mounted component using the chip carrier according to the present invention shown in FIG. 1, and FIG. Figures 13 (A) to (E) are explanatory diagrams of examples of changes in parts corresponding to the mounting structure and cooling structure for chip-mounted components using carriers.
14 is an explanatory diagram of a modified example of a chip mounting component configured by mounting a semiconductor chip on a chip carrier according to the present invention, and FIGS. ) are explanatory diagrams of different examples of modification, Fig. 15 is an explanatory diagram of a conventional chip carrier and its usage state, Fig. 15 (a) is a plan view of the conventional chip carrier, and (b) is the same side. A sectional view, (c) is an enlarged view of circle C in (a), and (d) is an explanatory diagram of the state in which the chip carrier is used. DESCRIPTION OF SYMBOLS 1...Chip carrier, 1a...Circuit board connection terminal, 1b...Circuit board connection surface, 1c...Chip connection terminal, ld...Chip connection surface, 2...Carrier board,
2C... Through hole for accommodating conductor, 2d... Through hole for accommodating resistor, 3.4... Thin film wiring layer, 5... Semiconductor chip, 8... Chip mounting component, 9... Circuit board , 12... High thermal conductivity plate, 13... Cooling plate, 21.
...Solder sealing part (sealing member) 1 Chip carrier
5 Semiconductor chip 7 Sealing resin 8 Chip mounting parts
9 Circuit board 12 High thermal conductor 13 Cooling plate Fig. 2 Chip carrier 1c Circuit board connection terminal 1b Circuit board connection surface 9 Circuit board Fig. 3 Fig. 5 2b, 102b, 202b Lower surface of carrier board 2c,
202C conductor housing through hole JL/2d, 202d resistor housing through hole 302 Carrier board 30
2a Carrier board top surface 302C Conductor accommodating through hole 302d Resistor accommodating through hole 402c Conductor accommodating through hole 402d Resistor accommodating through hole No. 9
Figure 10 2 Carrier board 2c Conductor accommodating through hole 2d Low resistance accommodating through hole 208, 308 Chip mounting parts
209,309 Circuit board 12 Figure 8 Chip Gosen parts 113,213/'f 9 Circuit board 113b Leg member 13 Figure 5 Semiconductor chip 8. Chinov tower a defective product 91 Circuit board Figure 13 (e) 5. Semiconductor chip sensor, chip tower mounting parts 97 Circuit board 712.712: High thermal conductive plate 713. Cooling plate 714, thermal conductive grease (c)
(2) 1 Chinov carrier 5 semiconductor chip 81.
82.83. B4 chip mounting parts Figure 15 (b) (:)

Claims (1)

[Claims] 1. A chip connection surface having a plurality of chip connection terminals connected to a semiconductor chip, and a plurality of circuit boards formed on the opposite surface of the chip connection surface and connected to a circuit board. A chip carrier having a circuit board connection surface having connection terminals, between the chip connection surface and the circuit board connection surface, there are a plurality of conductor accommodation through holes in which conductors are housed and a resistor therein. A carrier board having a plurality of resistor-accommodating through-holes is disposed, and the plurality of chip connection terminals and the plurality of circuit board connection terminals are connected to each other through the conductor-accommodation through-hole or the resistor-accommodation through-hole. A chip carrier characterized by being connected. 2. The chip carrier according to claim 1, wherein the carrier substrate is formed of a multilayer thick film. 3. A circuit board having a chip connection surface having a plurality of chip connection terminals connected to the semiconductor chip, and a plurality of circuit board connection terminals formed on the opposite side of the chip connection surface and connected to the circuit board. and a plurality of conductor-accommodating through-holes in which conductors are housed, and a plurality of resistor-accommodating through-holes in which resistors are housed, between the chip connection surface and the circuit board connection surface. a carrier board is disposed, and the plurality of chip connection terminals and the plurality of circuit board connection terminals are connected via the conductor-accommodating through-hole or the resistor-accommodating through-hole. 1. A chip carrier, wherein at least one of the connection surface and the circuit board connection surface is formed of a thin film wiring layer. 4. A circuit board having a chip connection surface having a plurality of chip connection terminals connected to the semiconductor chip, and a plurality of circuit board connection terminals formed on the opposite side of the chip connection surface and connected to the circuit board. and a plurality of conductor-accommodating through-holes in which conductors are housed, and a plurality of resistor-accommodating through-holes in which resistors are housed, between the chip connection surface and the circuit board connection surface. A carrier board having a chip carrier is disposed, and the plurality of chip connection terminals and the plurality of circuit board connection terminals are connected to a chip carrier via the conductor accommodation through hole or the resistor accommodation through hole, and this chip carrier. A chip mounting component comprising: a semiconductor chip face-down bonded to the chip connection surface of the chip; 5. A circuit board having a chip connection surface having a plurality of chip connection terminals connected to the semiconductor chip, and a plurality of circuit board connection terminals formed on the opposite side of the chip connection surface and connected to the circuit board. and a plurality of conductor-accommodating through-holes in which conductors are housed, and a plurality of resistor-accommodating through-holes in which resistors are housed, between the chip connection surface and the circuit board connection surface. A carrier board having a chip carrier is disposed, and the plurality of chip connection terminals and the plurality of circuit board connection terminals are connected to a chip carrier via the conductor accommodation through hole or the resistor accommodation through hole, and this chip carrier. a semiconductor chip face-down bonded to the chip connection surface of the chip mounting component, and a chip mounting component comprising: a semiconductor chip face-down bonded to the chip connection surface; and a semiconductor chip face-down bonded to the chip connection surface; A chip-mounted component characterized by having members arranged therein. 6. A circuit board having a chip connection surface having a plurality of chip connection terminals connected to a semiconductor chip, and a plurality of circuit board connection terminals formed on the opposite side of the chip connection surface and connected to the circuit board. and a plurality of conductor-accommodating through-holes in which conductors are housed, and a plurality of resistor-accommodating through-holes in which resistors are housed, between the chip connection surface and the circuit board connection surface. A carrier board having a chip carrier is disposed, and the plurality of chip connection terminals and the plurality of circuit board connection terminals are connected to a chip carrier via the conductor accommodation through hole or the resistor accommodation through hole, and this chip carrier. A semiconductor chip mounting structure characterized in that a semiconductor chip is face-down bonded to the chip connection surface of the semiconductor chip, and a plurality of chip mounting components comprising: are wirelessly bonded to a single circuit board. 7. A circuit board having a chip connection surface having a plurality of chip connection terminals connected to the semiconductor chip, and a plurality of circuit board connection terminals formed on the opposite side of the chip connection surface and connected to the circuit board. and a plurality of conductor-accommodating through-holes in which conductors are housed, and a plurality of resistor-accommodating through-holes in which resistors are housed, between the chip connection surface and the circuit board connection surface. A carrier board having a chip carrier is disposed, and the plurality of chip connection terminals and the plurality of circuit board connection terminals are connected to a chip carrier via the conductor accommodation through hole or the resistor accommodation through hole, and this chip carrier. a semiconductor chip face-down bonded to the chip connection surface of the semiconductor chip carrier; and a semiconductor chip mounting structure in which a plurality of chip-mounted components made up of the following are wirelessly bonded to one circuit board, the circuit board connection of the chip carrier. A semiconductor chip mounting structure characterized in that a sealing member is disposed in a gap between a peripheral edge of a surface and a circuit board facing the peripheral edge. 8. A circuit board having a chip connection surface having a plurality of chip connection terminals connected to the semiconductor chip, and a plurality of circuit board connection terminals formed on the opposite surface of the chip connection surface and connected to the circuit board. and a plurality of conductor-accommodating through-holes in which conductors are housed, and a plurality of resistor-accommodating through-holes in which resistors are housed, between the chip connection surface and the circuit board connection surface. A carrier board having a chip carrier is disposed, and the plurality of chip connection terminals and the plurality of circuit board connection terminals are connected to a chip carrier via the conductor accommodation through hole or the resistor accommodation through hole, and this chip carrier. In a semiconductor chip mounting structure in which a semiconductor chip is face-down bonded to the chip connection surface of the semiconductor chip, and a plurality of chip mounting components are wirelessly bonded to a single circuit board, A cooling plate is provided, and a thermally conductive member is interposed between the back surface of the semiconductor chip and the cooling plate for transmitting heat of the semiconductor chip to the cooling plate, and the thermally conductive member is made of thermally conductive grease. A semiconductor chip mounting structure characterized by having. 9. A patent characterized in that the thermally conductive member includes a highly thermally conductive plate that is disposed in contact with the back surface of the semiconductor chip and has a larger area than the back surface of the semiconductor chip, and thermally conductive grease. A semiconductor chip mounting structure according to claim 8. 10. A comb tooth-receiving recess is formed on the lower surface of the cooling plate, and the heat conductive member includes a high heat conductive plate having a comb tooth-like protruding member that is inserted into the comb tooth receiving recess, and thermally conductive grease. A semiconductor chip mounting structure according to claim 8, characterized in that it has the following. 11. A circuit board having a chip connection surface having a plurality of chip connection terminals connected to a semiconductor chip, and a plurality of circuit board connection terminals formed on the opposite side of the chip connection surface and connected to the circuit board. and a plurality of conductor-accommodating through-holes in which conductors are housed, and a plurality of resistor-accommodating through-holes in which resistors are housed, between the chip connection surface and the circuit board connection surface. A carrier board having a chip carrier is disposed, and the plurality of chip connection terminals and the plurality of circuit board connection terminals are connected to a chip carrier via the conductor accommodation through hole or the resistor accommodation through hole, and this chip carrier. A semiconductor chip is face-down bonded to the chip connection surface of the semiconductor chip, and a plurality of chip mounting components comprising: are wirelessly bonded to a single circuit board, and a cooling plate is further disposed above the back surface of the semiconductor chip. In the semiconductor chip mounting structure, a heat conductive member is interposed between the back surface of the semiconductor chip and the cooling plate for transmitting heat of the semiconductor chip to the cooling plate. By disposing leg members that airtightly seal the space between the peripheral edge of the cooling plate and the peripheral edge of the cooling plate, all of the plurality of chip-mounted components wirelessly bonded on the circuit board are disposed. A semiconductor chip mounting structure characterized by being sealed.