JPS63114174A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a short channel MOSFET easily by a method wherein an insulating film is laminated onto the surface of a trench formed on a semiconductor substrate, a conductive film is laminated onto the insulating film, a resist is applied, a gate electrode is formed only in the trench through etchback without using a mask, and impurity ions are implanted to the whole surface to form source and drain regions. CONSTITUTION:A polysilicon film 22 as a conductive film for a gate electrode and a resist 23 are applied onto the whole surface of an silicon substrate 11 to which a trench is shaped, the gate electrode 13 is formed only into the trench 21 without employing a mask through etching under conductions in which the etching rates of both the film 22 are the resist 23 are equalized, and the surface of an element can be flattened. Ions are implanted to the whole surface without using the mask when shaping source-drain region 15, thus simultaneously allowing the formation of the source-drain regions 15 and the lowering of the resistance of the gate electrode 13 consisting of polysilicon, etc. Accordingly, an excellent buried gate type MOSFET having short channel length is acquired easily.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and in particular to a method for manufacturing a semiconductor device.
) type MO8 (Metal Oxide Sem1con
) FF:T (field effect transistor)
It is related to.

(Prior Art) When the channel length of a MOSFET is shortened, problems arise such as a decrease in threshold voltage and generation of leakage current (short channel effect). For this reason, it is necessary to increase the impurity concentration in the channel, and to form shallow ion implantation layers in the source/drain regions to suppress the lateral extension of the depletion layer.

To solve this problem, a buried gate MO3FET with almost zero junction between the source and drain regions is proposed in the literature, Institute of Electronics and Communication Engineers Technical Research Report Vol. 1.86, A139. P59~
64. This manufacturing method will be explained using FIG. 2. First, as shown in FIG. 2 (6), after element isolation is performed using a silicon substrate 101 by the usual selective oxidation method (not shown), n-type impurity As is ionized into a predetermined region of the silicon substrate 101. The source/drain regions 102 are formed by implantation. Then, as shown in FIG. 2(b), a resist pattern 104 is formed on the oxide film 103, such as SiO□, deposited by CVD (chemical vapor deposition). Next, as shown in FIG. 2(C), Regis)/?
The oxide film 103 is etched by RIE (reactive ion etching) using the turn 104 as a mask, and after removing the resist turn 104, the nW impurity layer 102 is etched using the oxide film 103 as a mask.

Next, as shown in FIG. 2(d), after forming an r-t oxide film 105 on the surface of the silicon substrate 101 by thermal oxidation, as shown in FIG. 106 is formed. Next, after forming an intermediate insulating film 107, holes for contacts are formed in necessary parts, and finally an At electrode 10B is formed as shown in FIG. 2(f).

By the manufacturing method described above, the depth of the gate electrode and the source/drain region are almost equal, that is, the buried gate type MO8F has an apparently extremely shallow junction.
ET is completed. This embedded cage MOSFET
In this case, there is no need to make the diffusion of the source/drain region particularly shallow, and the apparent junction depth can be reduced to almost zero. For this reason, the depletion layer in the source/drain region becomes difficult to extend toward the channel side, and short-channel MOSFETs
This has the effect that ET can be easily realized.

(Problems to be Solved by the Invention) However, in such a buried gate MO8FET, a highly accurate mask alignment process is required in patterning the gate electrode, and the The structure is such that the apparent junction depth is zero by making the etching depth of the substrate equal to the impurity implantation depth of the source/drain regions, so it is extremely difficult to control both. If it becomes shallower than this, there will be a problem that an electrical short will occur between the source and drain regions, and furthermore, the gate electrode will be exposed above the surface of the substrate, making it difficult to planarize the device surface. There was a problem that it was not sufficient and multilayer wiring was difficult.

(Means for Solving the Problems) In order to solve the above problems, the present invention provides a buried gate type M
When manufacturing an O8FET, a groove is formed by etching a predetermined region of a semiconductor substrate, an insulating film is laminated on the surface including the bottom and side surfaces of this groove, and a conductive film for a gate electrode is laminated on this insulating film. After applying a resist flatly on this conductive film, etching back is performed without using a mask to remove the insulating film and the conductive film other than the groove, forming a gate electrode only in the groove, and etching the entire surface. By ion-implanting impurities into the structure and heat-treating it, source and drain regions are formed and the resistance of the gate electrode is reduced.

(Function) The present invention is a method for manufacturing a buried cage MO8FET, in which, for example, a silicon substrate with a groove is coated with a polysilicon film as a conductive film for a gate electrode and a resist,
By performing etching under conditions where both etching rates are equal, a gate electrode can be formed only in the groove without using a mask, and the element surface can be planarized. Furthermore, when forming the source/drain regions, by performing ion implantation over the entire surface without using a mask, it is possible to form the source/drain regions and lower the resistance of the gate electrode, such as polysilicon, at the same time. .

(Embodiment) FIG. 1 is a cross-sectional view for explaining a method of manufacturing a buried Y-type MOSF'ET according to an embodiment of the present invention, and the explanation will be given below along with the drawings.

First, as shown in FIG. 1(,), on a silicon substrate 11,
After a first insulating film, for example, an oxide film 20 such as 5i02, is deposited on the entire surface by a vapor phase growth method (CVD method), the portion where the groove is to be formed is removed, and the oxide film 20 is formed as shown in FIG. 1(b). After etching the silicon substrate 11 using 20 as a mask to create a trench 2, the oxide film 20 is removed.

Next, as shown in FIG. 1(c), a υ gate oxide film 12 is formed by a thermal oxidation method, and a polysilicon film 22 that will become a gate electrode is formed.
After depositing the resist 23 on the entire surface, a resist 23 is further applied evenly over the entire surface. Next, the entire surface is etched flat (etch pack) under conditions such that the resist 23 and the polysilicon film 22 have the same etching rate, such as sputter etching or ion etching using inert Ar gas. If the etching is stopped when the oxide film 12 is exposed, only the polysilicon film 22 in the trench remains, as shown in FIG. 1(d), and the gate electrode 13 can be formed. Furthermore, after forming a gate protection film 14 on the entire surface by thermal oxidation, impurity ions are implanted on the entire surface and heat treatment is performed to form a low resistance layer 15 that will become the source/drain region as shown in FIG. It is formed. At this time, ions are also implanted into the polysilicon of the gate electrode 13, thereby reducing the resistance. Finally, as shown in FIG. 1(f), an intermediate insulating film 16 is deposited, contact holes are formed, and metal electrodes 17 making ohmic contact are formed to complete the process.

As described above, according to the embodiment of the present invention, the r-t electrode 13
Since the formation is performed in a self-lined manner using an etch pack, there is no need for a mask alignment process, and there is no need to reserve excess Fi for mask alignment, thereby promoting miniaturization. In addition, since the ion implantation for forming the low resistance layer 15 that will become the source/drain region can be performed on the entire surface, it becomes a self-line, and like the gate electrode 13, the mask alignment margin and mask alignment process are unnecessary, and the fine This will lead to the promotion of At the same time, the gate electrode 13
Since impurities are also implanted into the polysilicon, the resistance of the gate electrode 13 can be reduced. Furthermore, since the gate electrode 13 is not exposed above the silicon substrate 11, the element surface is flat and flattening of the insulating film surface is promoted. Therefore, it becomes easy to form wiring made of aluminum or the like (not shown), and multilayer wiring becomes possible.

(Effects of the Invention) As described in detail above, according to the present invention, the gate electrode and the source/drain regions can be formed using the self-alignment line, making it possible to form a good buried gate type MO8 with a short channel length.
FETs can be easily manufactured and can be applied to large-scale integrated circuit devices.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are cross-sectional views of a buried gate MO8FET for explaining the present invention in detail, and FIGS.
) to (f) are cross-sectional views of a conventional buried gate type MO8FET. 11.101...Silicon substrate, 12...r-to insulating film, 13.106...gate electrode, 14...r-
15... Low resistance layer, 16.107... Intermediate insulating film, 17... Metal electrode, 20... Oxide film, 2
1... Groove, 22... Polysilicon film, 23... Resist. Patent Applicant: Oki Electric Industry Co., Ltd. A, 4\, Invention: July 5th!兇■Rusu rukume 4 1st noj! Cross-sectional HA diagram of MO5FET

Claims (1)

[Claims] A step of forming a groove by etching a predetermined region of a semiconductor substrate; a step of laminating an insulating film on the surface including the bottom and side surfaces of the groove; and a step of laminating a conductive film for a gate electrode on the insulating film. a step of stacking films; a step of flatly applying a resist on the conductive film for the gate electrode; and a step of etching back without using a mask to remove the insulating film and the conductive film for the gate electrode other than the groove. A method for manufacturing a semiconductor device, comprising: forming a gate electrode only in the groove; and forming source and drain regions by ion-implanting impurities over the entire surface and heat-treating the entire surface.