JPS63114172A - Integrated circuit - Google Patents

Abstract

PURPOSE:To form a low resistance connection in an integrated circuit without damaging an silicon substrate by forming first and second silicide paths directly being in contact with source and drain regions and forming passivation layers each having contact holes at the second end sections of the second silicide path. CONSTITUTION:A MOSFET is formed, an oxide side wall spacer 15 is shaped around a polysilicon-gate 20 on the spacer 15, and a layer consisting of a refractory metal 26 is attached uniformly onto a MOSFET element. An amorphous- silicon layer 25 is affixed equally onto the refractory metallic 26 layer, a pattern is formed to the amorphous-silicon layer 25, and the refractory metallic 26 layer and the amorphous-silicon 25 with the pattern are changed into an silicide through a thermal annealing process. A refractory metallic region 50 not- converted is removed, a self-alignment contact to source-drain by the silicide and a gate region is formed, a passivation layer 55 is annexed onto the contact, and a contact-hole is shaped and the metallic layer and an silicide layer can be brought into contact.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention generally relates to the structure of an integrated circuit, and the contact portion (
and methods of forming interconnects between integrated circuit devices.

[Prior art and its problems]

Figures 1A to 1C show conventional semiconductor integrated circuits, especially MO
It is a sectional view of SFET.

In the prior art, individual integrated circuit devices such as MOSFETs are typically shown in FIGS.
They are interconnected in the manner shown in Figure C. First, MOSF
The ET is fabricated on a semiconductor substrate by methods well known to those skilled in the art to form the structure shown in FIG. 1A. A passivation layer, such as phosphosilicate glass, is then deposited uniformly over the MOSFET and the MOS
Etch through the passivation layer above the FET source and drain to form contact holes. 1st C
As shown, a metal layer, for example an aluminum alloy, is deposited over the passivation layer to make contact with the source and drain of the MOSFET through contact holes. Finally, backs are created in the metal layers to properly interconnect the various MO5FETs of the integrated circuit.

Although this prior art method is suitable at first glance, it is becoming less suitable as device dimensions become smaller and smaller. For example, the conventional method shown in FIGS. 1A to 1C Also, undercuts occur during etching of the contact area.As a result, the MOS F E
A T-element requires a gap between its source and drain contact holes and the edges of the polysilicon gate and field oxide. This extra space requirement creates waste in the integrated circuit, increases junction capacitance, and limits integrated circuit density. Furthermore, the contact resistance increases due to the space between the contact hole and the edge of the active device, thus further reducing device performance.

Several approaches have been proposed to overcome the problems of the prior art. For MOS FET devices, one approach is to contact the source and drain regions using a polysilicon layer to minimize the junction area. This method is illustrated in Figure 2.The connection between the polysilicon layer and the metal layer is then formed on the field oxide layer.The major disadvantage of this method is that during the etching of the polysilicon, the silicon substrate It is also possible to be etched by carelessness.

Therefore, the effective junction depth may be affected and the substrate may also be damaged. Another disadvantage of the method shown in FIG. 2 is that the polysilicon layer is not a particularly good conductor and therefore creates a significant resistance between the metal contact and the source or drain region.

The method shown in FIG. 3 addresses the problem of contact resistance.

To reduce resistance, a refractory metal such as titanium is uniformly deposited onto the polysilicon, then annealed to form a resistive silicide, followed by removal of unreacted refractory metal. . Unfortunately, the method illustrated in the structure shown in FIG. 3 still has the potential to damage the silicon substrate during etching of the polysilicon layer. Furthermore, the polysilicon layer is MOSF
Since it is used to contact the source and drain of the ET, the method of Figure 3 should only be used if the crystal structure, polarity, and doping levels to the polysilicon source and drain are closely matched. I can't. If the polysilicon properties described above are not precisely matched, large contact resistances and parasitic diode effects may occur, possibly impairing device operation.

There have been several attempts in the prior art to use silicides as ohmic contacts. For example, Mr. U discloses an ohmic contact for a small, shallow structure element in the ``rlBM Technical Disclosure Bulletin'' Volume 22, No. 4 (September 1979). It is made by disposing a metal layer on the membrane, disposing a polysilicon layer on the metal layer, patterning the polysilicon, and reacting the patterned polysilicon with the underlying metal layer to convert it to a silicide.

A problem with Ku's method is that it is difficult to form a polysilicon layer over a metal layer. When two layers are formed by low pressure chemical vapor deposition (LPGVD), the LPGVD machine is
It must be evacuated twice, once for metal deposition and once for high temperature polysilicon deposition.

Furthermore, Ku does not consider the issue of connecting the silicide layer to the silicon layer. Ku's silicide is formed entirely on a metal layer, and the metal layer is formed entirely on a dielectric layer. In fact, the problem of connecting silicide layers to silicon layers is not generally well addressed in the prior art. Current technology only allows n-type polysilicon-based silicides to be connected to n-type acon layers without the aforementioned problems of high ohmic contact and parasitic diode effects. Clearly, such silicide to silicon connections are inappropriate for P-channel O8 or CMO3 environments.

[Purpose of the invention]

It is an object of the present invention to make low resistance connections for integrated circuits without damaging the silicon substrate.

Another object of the invention is that MOS FET devices can be made with smaller source and drain regions, in other words, the area of the source and drain regions can be reduced;
The goal is to increase the density of integrated circuits.

Yet another object of the present invention is to allow devices to be bonded together without the need for metal layers and to allow connections to gold J71 to be shared by several devices.

Yet another object of the present invention is to create a low resistance silicide connection that can contact and interconnect virtually any type of integrated circuit device.

Yet another object of the invention is to provide low resistance interconnects and contacts in a simple and inexpensive manner.

Yet another object of the invention is to connect multiple devices to a metal layer with a single, common contact.

Yet another object of the invention is to enable the silicide layer to contact and interconnect virtually any type of integrated circuit device.

[Summary of the invention]

In accordance with the method of the present invention, a MOSFET is fabricated and then oxide sidewall spacers are formed around its polysilicon gate. Next, a layer of refractory metal is coated with MO3FE.
A layer of amorphous silicon is then deposited uniformly over the refractory metal layer. The amorphous silicon layer is patterned by etching, using the refractory metal as an etch stop to prevent inadvertently etching the underlying silicon substrate. The refractory metal layer and patterned amorphous silicon are then converted to silicide through a thermal annealing process. This process completely consumes amorphous silicon. The unconverted refractory metal region is then removed and the silicide source
Create self-aligned contacts to the drain and gate regions. A passivation layer is uniformly deposited over the silicide layer and etched to form contact holes through the passivation layer to allow contact between the metal layer and the silicide layer.

These and other objects and advantages of the present invention will become apparent to those skilled in the art from reading the following description and studying the figures in the drawings.

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 4A to 4D illustrate a method of manufacturing integrated circuits, in particular a method for making contacts to MOSFET devices, according to the present invention.

According to the invention, an integrated circuit device 10, for example a MOS
FET devices are fabricated by conventional methods. Next, oxide wall spacers 15 are formed to polysilicon gate 20. This spacer 15 is formed by chemical vapor deposition (CVD).
) can be formed by anisotropically etching a homogeneous layer of silicon dioxide. Next, refractory metal 2
6. A composite layer of amorphous silicon 25 on it,
Sputter deposit onto the elements including spacers 15.

More specifically, a refractory metal 26 is first deposited uniformly over the device, and then amorphous silicon 26 is deposited uniformly over the refractory metal 26. Deposition of the first metal 26 and then the silicon 25 can be accomplished in one evacuation cycle of the sputtering apparatus by providing both a metal target and a silicon target within the sputtering machine.

Next, using a mask (not shown), the amorphous silicon 25 is etched into a predetermined pattern.

The underlying refractory metal layer 26 serves as an effective etch stop during this patterning process to avoid damage to the underlying substrate. Additionally, the amorphous silicon layer 25 is completely separated from the underlying substrate by the metal layer 26 to prevent possible crystal growth into the substrate.

After patterning, device 10 is subjected to a thermal annealing cycle to provide a refractory film in direct contact with the source, drain region 35 and gate region 20 of device 10, and region 45 with patterned amorphous polysilicon layer underneath. Forms metal silicides. Next, area 5 of unreacted refractory metal
Selectively remove 0s. If the refractory metal is titanium, it can be removed, for example, by selective chemical etching.

Finally, a passivation layer 55 is deposited, contact holes 60 between refractory metal silicide 30 and metal 65 are defined above passivation layer 55, and metal 65 is
is deposited and buttered to form a contact to the silicide layer exposed in hole 60.

In fact, in the method according to the invention, the refractory metal silicide layer 30
enables the formation of self-aligned contacts to the source, drain region 35 and gate region 20 of the MOS FET device. According to an illustrative embodiment of the invention, MO5FE
In the case of a T-element, the area of the source and drain regions 35 is minimized because the contact to the source and drain regions 35 does not depend directly on contact holes 60 defined in the passivation layer 55 as in the prior art. be able to.

This reduces junction capacitance and enables denser integrated circuits.

Furthermore, in the present invention, the low resistance silicide layer can also be used to interconnect several devices, so that the contact from the silicide layer to the metal layer can be shared among multiple devices. Out. This reduces the number of contacts within the integrated circuit, increases puffing density, and improves yield.

Referring now to FIG. 5, hypothetical exemplary integrated circuit structure 10
0 will be used to describe the method of local interconnection of integrated circuit elements. For example, the first element 102 and the second element
104 are formed on a semi-thin substrate 106 and separated by a portion of field oxide 10B. Element 102
and 104 are similarly separated from other adjacent devices by other field oxide portions, such as portions 110 and 112.

For purposes of illustration, assuming substrate 106 is of P-type material, first device 102 is an n-channel MOS.
It can represent a transistor.

A pair of n-doped regions 114 and 116 can serve as a source or drain, and a polysilicon gate 118 is separated from a channel region 120 by a thin oxide layer 122. The second device 104 is a P-channel MOS transistor with a structure consisting of an N-type well 124, n-doped regions 126 and 128, and a polysilicon gate 13o separated from channel region 132 by a thin oxide 134. .

First IC device 102 and second IC device 104 are shown locally connected by a conductive path 136 extending above field oxide 108 .

Conductive path 136 is preferably a silicide formed by the previously described method of the present invention, but may also be a metal path such as titanium tungsten (TiW) or titanium nitride (TiN). An advantage of using silicide for conductive path 136 is that it is easy to etch without damaging substrate 106.

Conductive path 136 has a first end 138 in contact with region 116 of element 102 and a second end 140 in contact with region 126 of element 104. Therefore, due to the physical orientation of the respective elements 102 and 104, the conductive path 136 is between the sources and drains of the MO3I transistors, between the sources of the MO3I transistors, and between the sources of the MO3I transistors;
The drains of the oS transistors can be coupled.

Also shown in FIG. 5 is a second conductive path 142, which, like conductive path 136, is preferably made of silicide, but could also be made of any suitable metal or metal alloy. When made from silicides, they can be produced by the above-described method of the invention. Conductive path 142 has a first end 144 that contacts region 114 of element 102;
There is a second end 146 in contact with a polysilicon gate 148 that is part of an adjacent MOS transistor (not shown). This means that the standard CMOS cell is
is a particularly advantageous interconnect structure for 0MO3 devices since it couples the sources and drains of a complementary MOS transistor pair to the gates of a second complementary MO3I transistor pair.

It is important to note that the method of making conductive silicide paths of the present invention allows regions of opposite polarity types to be bonded together. For example, conductive silicide path 136 can couple n-doped region 116 to n-doped region 126.

To do this, amorphous silicon on refractory metal must be used to form the silicide.

This is because polysilicon-based silicides produce very high ohmic contacts and can also form parasitic diodes.

Other conductive paths, such as paths 150 and 152, may also be formed as part of the process of forming conductive paths 136 and 142. These paths couple gates 118 and 120 to other devices and metals.

A passivation layer 154 made of a suitable material such as silicon dioxide may be formed over IC structure 100 and a contact hole, such as contact hole 156, may be etched through passivation layer 154. Gold IN 158 can then be formed and patterned over the field oxide portions 108 and in contact with the conductive paths 136.

As previously noted, by forming contacts over portions of field oxide, the MOSFET devices can be made smaller, increasing the density of the integrated circuit.

It should be noted that numerous publications detail the general techniques used in the fabrication process of integrated circuit components. For example, Breston (Pres.
"Semiconductor and integrated circuit manufacturing technology J" published by ton) Publishing Co., Ltd.
Integrated C1rcuit Fabric
ation Techniques). These techniques can generally be utilized in fabricating the structures of the present invention. Moreover, the individual manufacturing steps can be performed using commercially available integrated circuit fabrication machines.

Although the invention has been described in terms of several embodiments, various modifications and substitutions of the invention will become apparent to those skilled in the art from reading the foregoing description and studying the drawings. For example, the method according to the invention can be applied to P-channel and n-channel MO
Equally applicable to SFET. It is also possible to apply this self-aligned contact technique to other types of devices such as bipolar transistors.

〔Effect of the invention〕

As can be seen from the foregoing description, the present invention can provide low resistance interconnects within integrated circuits without damaging the substrate, can provide small area source/drain regions, and can provide metal layers. It is possible to provide an integrated circuit in which elements can be connected to each other without using.

[Brief explanation of the drawing]

Figures 1A, 1B and 1C are MOS FETs.
FIG. 2 is a diagram showing the conventional method of forming a contact part for
Figure 3 shows another conventional method of forming a contact part for an OSFET. Figure 3 shows another conventional method of forming a contact part for a MOS FET, and shows a method improved from the method shown in Figure 2. , 4A to 4D, and 5 are cross-sectional views of a MOS FET according to the present invention. 10: MOSFET, 15: Oxide wall spacer, 20
: polysilicon gate, 26: refractory metal, 25: amorphous silicon, 30: refractory metal silicide, 55: passivation layer, 6
5: metal, 100: IC1 108, 110, 112: field oxide, 118,
130: Polysilicon gate, 136, 142.14
0: Conductive path, 156: Contact hole, 158
: Metal layer, 106: Semioligosubstrate

Claims (1)

[Claims] a first silicide path having a first end in direct contact with the source region and a second end of a portion extending from the first end; a second silicide path having a first end and a second end of a portion extending from the first end, the source and drain regions being formed on the first and second silicide paths; a passivation layer having a first contact hole at a second end portion of the first silicide path and a second contact hole at a second end portion of the second silicide path.