JPH02224225A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To form a high melting silicide layer stably and obtain a semiconductor device free from junction leakage by a method wherein Si is preliminarily deposited with a small thickness before a silicide wiring process. CONSTITUTION:Silicon is preliminarily deposited as the under layer of a high melting point metal layer 109 before a silicide wiring process. In other words, the high melting point metal layer 109 is held between upper and lower non- doped amorphous silicon layers 108 and 110. With this constitution, unstable direct reaction between the high melting point metal layer 109 and diffused layers 106 and 107 having high impurity concentration is avoided and the stability of silicide reaction is improved. Moreover, as a distance between a junction depth and a high melting point metal silicide boundary is increased by the thickness of a lower amorphous silicon layer 112, the concentration of high melting point metal impurity contained in the depletion layer of a junction part can be reduced and a junction leakage current can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for forming wiring used in a semiconductor integrated circuit using a high melting point metal silicide layer.

[Conventional technology]

Generally, when scaling down an MO8 integrated circuit to improve the degree of integration, it is important to not only reduce the dart length and dart width of a MOS transistor (MO8T), but also to reduce the total wiring and contact area.

Figure 2 shows A New Device Intercon.
nect SchemeFor Sub-Micron
VLSI”IEDM 1984 Technical
This is a conventional wiring manufacturing method of this type proposed in DigestppH8-121. This is the connection between NMO8T and PMO8T that often appears in CMO8 integrated circuits.
This is achieved by directly using high melting point metal silicide wiring instead of wiring. This silicide wiring process? explain.

First, according to the commonly used CMOS process,
An N-well region 201f for PMO8T is formed on a P-type silicon substrate 200, and a field oxide film 202 which becomes an element isolation region is formed using the LOCO8 method.

Subsequently, a gate oxide film 203 and a gate polysilicon 204 are grown and patterned to form a dirt region. In addition, sidewall 205 is added to the sidewall of the dirt.
F is formed, and N-type impurities (As, P, etc.) 1- are implanted into the source and drain regions of NMO8T, and P-type impurities (B, etc.) are ion-implanted into the source and drain regions of PMO8T. N+ source/drain diffusion layer 206. A P+ source/drain diffusion layer 207f is formed. (Figure 2(a)).

Next, a high melting point metal layer 208 and an amorphous silicon layer 209'f: are deposited on the entire surface of the substrate 200 by the Nupatta method or the like, and an N+ source/drain diffusion layer 2 of NMO8T is deposited.
P+ source/drain diffusion layer 207 of 06 and PMO8T
Connect with. Then, only the wiring portion is covered with a photoresist or the like 210, and the amorphous silicon layer 209 other than the wiring portion is etched away by dry etching or the like. Here, the high melting point metal layer 20B is 200 to 100O
The one with a thickness of about X is an amorphous silicon layer?
A thickness of approximately 500 to 2,000X is typically used (Fig. 2(b)).

Furthermore, after removing the 21θ etching mask such as the photoresist described above, the amorphous 7 silicon layer 209 and the high melting point metal layer 20B are subjected to high temperature heat treatment, typically 600°C.
A chemical reaction is performed at about 800° C. to form a high melting point metal silicide layer 220f.

The dirt region 21 is formed by the reaction between the high melting point metal layer 208 and the gate polysilicon 204, and the source/drain region 212 is formed by the reaction between the high melting point metal layer 20g and the silicon substrate 200 of the P north/villain diffusion layer 207. A high melting point metal silicide layer 220 is formed by reaction with the upper amorphous silicon layer 209, and in the wiring region 213 covered with the photoresist 210 by reaction with the upper amorphous silicon layer 209. Note that since the sidewall 205 made of S + 02 exists in the region 14 of the sidewall 205, the high melting point metal layer remains without undergoing the silicidation reaction. Therefore, the remaining metal layer is selectively removed by selective wet etching according to a normal silicide wiring process (FIG. 2(C)).

Thereafter, according to the normal CMO8 process, the intermediate insulating film 21
5 is deposited, a contact hole 216f is formed in the intermediate insulating film 215 on the wiring region 213, and the A? Turning is performed (Figure 2 (d)).

[Problem to be solved by the invention]

However, the conventional silicide wiring process described above has the following two problems.

(1) In source/drain diffusion layers with high impurity concentration,
A relatively thick native oxide film is present. This depends on the impurity concentration, but is typically around 230X. Due to the presence of this natural oxide film and the reaction with the high concentration impurity itself in the diffusion layer, it is difficult to carry out a stable silicidation reaction.

f2) Same L<Even if a high melting point metal silicide layer is formed in the source/drain region, high melting point metal atoms will diffuse into the diffusion layer of the source/drain region during the silicidation reaction. The high melting point metal impurities diffused into the silicon substrate increase the junction rift and deteriorate the Devine characteristics.

The purpose of this invention is to prevent the instability of the silicidation reaction, which is the drawback of the conventional method mentioned above, by pre-depositing a thin layer of 5t (5t) prior to the silicidation wiring process, and to prevent the bonding caused by high melting point metal impurities diffused into the silicon substrate. It is an object of the present invention to provide a method for manufacturing a semiconductor device that eliminates leakage, stably forms a high melting point metal silicide layer, and has less junction leakage.

[Failure to solve the problem]

The method for manufacturing a semiconductor device of the present invention is a method for manufacturing a semiconductor device such as an MO8 integrated circuit in which a plurality of diffusion layers formed by doping a substrate with high concentration impurities are interconnected using high melting point metal silicide. A non-dawg lower silicon layer is formed thereon, and then a refractory metal layer is formed on this silicon layer.

Then, the high melting point metal layer and the silicon layer are reacted,
The above-mentioned high melting point metal silicide gold is formed to form interconnections between the diffusion layers.

[Effect]

In order to carry out a stable silicidation reaction, a high melting point metal may be reacted with pure silicon. Furthermore, in order to reduce the diffusion of high melting point metal atoms into the diffusion layer during the silicidation reaction, the distance between the diffusion layer and the high melting point metal silicide interface is increased. The present invention has been made based on these findings.

When a lower silicon layer of NO/DOG is formed on a substrate to be processed on which a diffusion layer is formed, the distance between the diffusion layer and the refractory metal silicide interface increases by the thickness of the silicon layer.

〔Example〕

The following is the first embodiment of the present invention? This will be explained using FIG.

FIG. 1 is a manufacturing process diagram showing a method for manufacturing a semiconductor device according to a first embodiment of the present invention.

First, according to the normal CMO8 process, an N well region 101 for PMO8T is formed on a P type silicon substrate 100, and an L
A field oxide film 102, which will become an element isolation region, is formed using the OCO8 method or the like. Subsequently, dirt oxide film IOS and raw polysilicon 1041J (iJ?) are grown.
Turn to form a dirt area.

Furthermore, sidewalls 105 are formed on the side walls of the dirt, and N-type impurities (As, P, etc.) are added to the source/drain regions of NMO8T, and P-type impurities (B, etc.) are added to the source/drain regions of PMO8T. N+ source/drain diffusion layers 10 of each MO8T are formed by ion implantation, etc.
6. A P north drain diffusion layer 107 is formed.

(Figure 1(a)).

The process up to this point is exactly the same as the conventional process shown in FIG. 2 (,).

Next, the substrate to be processed 100 is subjected to normal reverse scrubbing and leaned, and then heated to a thickness of approximately 50 to 500X in Si f 10' Torr in Ar.
'It is deposited by the ivy method or the like to form a non-doped amorphous silicon layer 1081. Komude Siwo especially 50~
The reason for choosing 500X is as follows.

If it is thicker than 500X, St that does not contribute to the reaction will remain as polysilicon during the silicidation reaction, which will be described later, and the increase in wiring resistance will become unignorable, which is not desirable. On the other hand, if it is thinner than 50X, the effect of suppressing the diffusion of high melting point metal into the diffusion layer during the silicidation reaction becomes small, which is not desirable. Then, on top of this lower amorphous silicon layer 10g, a layer with a thickness of 200 g is added.
A high melting point metal layer 109f of ~1000X is similarly deposited by sputtering or the like. As the high melting point metal 109, No.
.

Although W or the like can be used, Ti, Ta, and Co are preferable in terms of reactivity with St and specific resistance of silicide. Next, Si with a thickness of about 200~100OX
Suno J? Then, a non-doped upper amorphous silicon layer 110f is formed (FIG. 1(b)).

At this time, it is necessary that the upper and lower amorphous silicon layers 108 and 110 sandwiching the high melting point metal layer 109 are non-doped, and that the above steps are performed continuously in the same sputtering apparatus without exposing the substrate 100 to the atmosphere. conduct. In addition, since the effect of oxygen such as a natural oxide film can be reduced, the silicidation reaction by high temperature heat treatment in the next step can be carried out stably.

Furthermore, using photolithography technology, only the connection wiring portion connecting the N+ source/drain diffusion layer 106 and the P+ source/drain diffusion layer 107 is covered with a 7 photoresist 111, and using this as a mask, the area other than the wiring area is covered. Upper amorphous silicon layer 110. High melting point metal layer 1o9. RIE (Reactive Ion Etchi) that can reduce the lower amorphous silicon layer to 10 gf
ng ), etc. (Figure 1 (C))
.

After that, RTA (Rapid Thermal Annealing) was performed in N2 atmosphere to eliminate the intrusion of atmospheric components.
l), etc., by performing high temperature heat treatment at 9600 to 8006C for about 10 to 60 seconds, and by reaction with the upper and lower amorphous silicon layers 108 and 110 sandwiching the high melting point metal layer 109f, the high melting point metal silicide layer 112f is formed. form (first
Figure (d)).

Here, the high melting point metal layer 1 which is the problem of the unexploded BJ8J
Diffusion into the diffusion layers 106 and 107 in the silicon substrate 100 of 09 depends on various factors such as high temperature heat treatment conditions, silicon substrate surface condition, sputter deposition conditions, impurity and defect concentration in the diffusion layer, and stress due to the high melting point metal silicide layer formed. This diffusion cannot be completely eliminated, although it varies depending on the However, the lower amorphous silicon layer 10B
The diffusion can be reduced by approximately the thickness of the film.

Note that Si that did not contribute to the reaction remains as polysilicon 113 on the formed refractory metal silicide layer 112, but this does not pose a particular problem.

Next, according to the usual process, an intermediate insulating film 114 is deposited, a contact hole is formed in this, and a wiring is formed using At or the like 115 (FIG. 1(e)).

As described above, according to the manufacturing method of the first embodiment, the upper and lower parts of the high melting point metal layer 109 are sandwiched between the thin films of the non-dawg amorphous silicon layers 108 and 110, so that the high melting point metal layer 1θ9 and a diffusion layer 106 with a high concentration of impurity gold. An unstable reaction with IO2 will not occur directly, and therefore, it can be expected that the stability of the silicidation reaction will be improved.

At the same time, for a junction with the same junction depth, the distance from the junction depth to the high-melting point metal oxide interface increases by the thickness of the underlying amorphous silicon layer 112. The metal impurity concentration can be reduced, and as a result, the junction leakage current can be reduced.

In particular, a non-doped amorphous silicon layer 10B,
High melting point metal layer 109. Upper amorphous silicon layer 1
105 by forming them continuously in the same equipment,
Since the effect of oxygen such as natural oxide film can be reduced, is it possible to use silicidation reaction by high-temperature heat treatment? - Layer stabilization is possible.

In addition, before forming the non-dawg amorphous silicon layer 108, the substrate 100 to be processed is cleaned by reverse sputtering in the same apparatus, thereby eliminating contamination caused by impurities in the diffusion layer that causes junction leakage current. can be further reduced.

As described above, according to the first embodiment, a high melting point metal silicide layer as a circuit wiring can be stably formed, so that miniaturization of a semiconductor integrated circuit can be made more effective.

Next, a second embodiment of the present invention will be described.

FIG. 3 is a manufacturing process diagram showing a second embodiment of the present invention. First, as in FIG. 1(,), leak drain regions of both P and N channel transistors are formed according to the normal CM)S process. (Fig. 3(a)) Next, as shown in Fig. 3(b), a Si film with a thickness of about 500-1000X is
A thin film 308 is formed. In this case, even with the commonly used LPCVD method, amorphous St.
Alternatively, polycrystalline Si is also possible.

Next, as shown in FIG. 3(c), using photolithography technology, only the connection wiring portion between the resistance region 306 and the P+ region 307 is covered with photoresist 309, and using this as a mask, the Si layer other than the above wiring region is covered. 308 f
RIE (Reactive Ion Etching)
) etc. to remove by etching. The end point of the etching is that most of the area other than the wiring area is the field oxide film 30.
2 and can be easily detected using conventional endpoint detection. Further, the photoresist 311 is also removed before the high melting point metal is deposited, and can be easily and stably removed by ordinary 02 plasma ashing or thermal H2SO4/H2o2.

Photoresist 311f - After removal, high melting point metal 309f
The silicon 3.08 and the refractory metal 309 are deposited by the Sunoyatsuta method (Fig. 3(d)) at a temperature of about 200-1000X, followed by a heat treatment in an N2 atmosphere (typically 600 -800 or higher) to cause a chemical reaction, high melting point silicide 312'
f:, form. Here the sidewall 5i023o5
The upper high melting point metal 309 does not undergo the silicidation reaction and remains as a high melting point metal. Therefore, by normal wet etching, only the high melting point metal can be selectively etched, leaving the high melting point silicide 311 selectively to form the wiring (the third
Figure (e)).

Next, as shown in FIG. 3(f), an intermediate insulating film 314 is deposited according to the usual 0MO8 process, a contact hole is formed, and a /J? We will do turning.

In the embodiment shown in FIG. 2, the following two
There are two advantages.

One problem is the selection ratio between amorphous silicon and the underlying high-melting point metal in the dry etching process. In the CF4-O2 gas system generally used for etching amorphous silicon, it is necessary to detect high melting point metals and stop etching, but it is not possible to increase the selectivity between amorphous silicon and high melting point metals.
Part of the high melting point metal is etched and becomes thin.

As a result, the first embodiment had a problem in that the resistance of the diffusion layer and the resistance of the dirt electrode increased.

However, in the second embodiment, the field oxide film is used for detecting the end point, so the selection ratio is large and the end point can be easily detected.

The second problem is that it is difficult to remove the resist used as a mask material during dry etching of amorphous silicon. Since high melting point metals are chemically active and have low chemical resistance, it is difficult to use ashing using 02f plasma or removal using thermal H2So4/H202, which are commonly used for resist removal. The first embodiment had a problem in that the removal method using an organic solvent such as acetone produced a resin residue with some high melting point metals (Ti, CO, etc.) and was unstable in terms of process.

However, in the second embodiment, since the resist If is removed before the high melting point metal is formed, the resist can be removed without leaving any resin and without damaging the high melting point metal.

〔Effect of the invention〕

According to the present invention, prior to the silicidation wiring process,
Since silicon is preliminarily formed under the high melting point metal layer, the high melting point metal silicide layer can be stably formed and junction leakage can be reduced as much as possible.

[Brief explanation of the drawing]

FIG. 1 is an illustration of the method for manufacturing a semiconductor device of the present invention.
00, 300 is a P-type silicon substrate, 106° 306 is a source/drain resistant diffusion layer, 107, 307 is a P+ source/drain diffusion layer, 108, 308 is an amorphous silicon layer below No/Dog, 109° 309 is a A high melting point metal layer 110 is a non-doped upper amorphous silicon layer, 112 and 312 t'i high melting point metal silicide layers, and 115 and 315 are wirings such as At. Fig. 1 Manufacturing process diagram showing conventional example Fig. 2

Claims (2)

[Claims] (1) A method for manufacturing a semiconductor device in which a plurality of diffusion layers formed by doping a semiconductor substrate with high-concentration impurities are interconnected using high-melting point metal silicide, which includes the steps of forming a lower silicon layer on the substrate; A step of forming a high melting point metal layer on the lower silicon layer, a step of forming an upper silicon layer on the high melting point metal layer, and a step of causing the high melting point metal layer to react with the upper and lower silicon layers sandwiching it. A method for manufacturing a semiconductor device, comprising the step of forming the high melting point metal silicide. (2) In a method for manufacturing a semiconductor device in which a plurality of diffusion layers formed by doping a semiconductor substrate with high-concentration impurities are interconnected using refractory metal silicide, only the wiring planned area on the substrate where the diffusion layer is formed is used. a step of selectively forming a Si layer; a step of forming a high melting point metal layer on the entire surface of the substrate including on the Si layer; and a step of reacting the Si layer and the high melting point metal layer to form a high melting point metal silicide. 1. A method for manufacturing a semiconductor device, comprising the steps of: