JPS63102341A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To provide a sidewall having a vertical surface which rose from the surface of a substrate with an electrical connection even in case a wiring layer of a proper level can not be utilized by a method wherein the sidewall is formed in a state that the insulating film of a part to be connected to the sidewall is selectively removed. CONSTITUTION:In order to remove an oxide film on the side surfaces of a poly Si pattern 12 to be connected to a sidewall, a poly Si pattern 11 on the other side is coated with a photo resist layer 15. The oxide film 14 on the side surfaces of the poly Si pattern 12 is removed using the photo resist layer 15 as a mask. As the oxide film of the unnecessary parts is completely removed at this amount of etching treatment, the etching treatment is executed to a degree that an oxide film of 700Angstrom is etched away. The photo resist is removed, an impurity-doped poly Si layer 16 is deposited by a CVD method and when an RIE is performed, the sidewall is formed on the side surface of the poly Si pattern, but this is electrically connected with the poly Si pattern 12 at parts where the oxide film on the side surfaces is removed.

Description

[Detailed Description of the Invention] [1 Remarks] In order to use a polycrystalline silicon (hereinafter referred to as polySt) sidewall deposited on a vertical surface of a semiconductor substrate as a part of an element or wiring, electrical current is applied to the sidewall. A method of forming a connection is disclosed.

The vertical surfaces are covered with an insulating film, and the insulating film is removed from the portions that should be electrically connected to the sidewalls. A poly-Si layer was deposited by CVD method and reactive ion etching (hereinafter referred to as
When the sidewall is formed by RIB), the conductor having the vertical surface from which the insulating film has been removed and the poly-Si sidewall are electrically connected to each other.

[Industrial application field]

The present invention relates to poly-Si used for forming elements of integrated circuit devices.
Relates to the method of providing electrical connections to the sidewalls.

In recent years, CVD deposition with good coverage and RIE, a highly directional etching method, have been developed, and in the same way that oxide and poly-Si layers are selectively formed on the horizontal surfaces of the substrate, they can be selectively formed on the vertical surfaces of the substrate. It is now possible to form

The poly-Si layer formed by covering the vertical surfaces by this method is called a sidewall, and is used, for example, to form an LDD structure MOS transistor shown in FIG. In the device shown in the drawing, 30 is a Sii board, and two S/Ds 31 are provided. This S/D diffusion is formed by first introducing impurities near the gate by shallow ion implantation using the gate electrode 32 as a mask, then forming sidewalls 33 on the sides of the gate electrode and performing deep ion implantation.

Normally, the sidewall is often used as such an auxiliary means, but it is also possible to use it as an element constituent material. In that case it is necessary to provide electrical connections, except for those used in the floating state.

[Conventional technology]

The grooves formed on the sides of the grooves excavated by RIE are arranged on a horizontal plane at the height of the substrate surface! Although it is possible to connect to the vI layer, there is still no known method of connecting to a vertical sidewall rising from the substrate surface that is highly usable.

[Problems to be Solved by the Invention] It is an object of the present invention to provide a method for providing electrical connections to vertical sidewalls rising from the substrate surface even when an appropriate level of wiring layer is not available. and
In particular, it is an object of the present invention to provide a method for connecting poly-Si patterns and sidewalls.

[Means for solving problems]

In order to achieve the above object, the present invention covers the side surfaces of a poly-Si pattern with an insulating film, and forms a sidewall by selectively removing the insulating film from a portion to be connected to the sidewall.

[For production]

An insulating film is interposed in the vertical plane of the substrate surface that must be insulated from the sidewall, and in areas where electrical connection is required, the sidewall is formed without the intervening insulating film. As a result, sidewall and poly S
1 pattern is connected.

〔Example〕

FIG. 1 shows the steps of an embodiment of the invention. The diagram is a schematic diagram showing the process of connecting the poly-Si pattern and the sidewall, and consists of a plan view and a cross-sectional view of each step of the process. 1
0 is a Si substrate with two poly-Si patterns 11.1
2 is provided on the substrate. Here, the process of connecting the sidewall formed around the poly-Si pattern 11 and the poly-Si pattern 12 will be explained.

As shown in the plan view (a) and cross-sectional view (a') of the same figure, two polyS S formed on the surface of the 3i substrate 10
An oxide film 13 with a thickness of approximately 3000 nm is observed on the top surfaces of the i-patterns 11 and 12. Although it is normal for an insulating film to exist between the poly-Si patterns and the substrate, this It is omitted in the drawing. In addition, the relationship between the cross-sectional view and the plan view in the figure is as follows (b) to (d) and (b') to (d'
) but the same is true.

This is thermally oxidized, and as shown in FIGS.
form.

Next, poly-Si pattern 1 to be connected to the sidewall
In order to remove the oxide film on the second side surface, the other poly-Si pattern 11 is covered with a photoresist layer 15. In this case, it is desirable that the pattern 12 is outside the photoresist layer, but since it is necessary to completely cover the pattern 11 with the photoresist, the photoresist layer is formed to be rather wide, and the tip of the pattern 12 is uniform. Parts are coated with photoresist. This state is shown in Figures (c) and (C').

Using the photoresist layer 15 as a mask, the oxide film 14 on the side surface of the poly 3i backcoon 12 is removed. The amount of etching is enough to remove the oxide film of 700 people in order to completely remove the oxide film from unnecessary parts.
The oxide film 13 on the upper surface of the poly-Si pattern 12 is also slightly etched, but it is sufficiently thick so that it does not interfere with subsequent steps. Note that this etching process is isotropic.

Remove the photoresist and remove the impurity-doped poly-Si
When a layer is deposited by CVD and subjected to RIE, a sidewall is formed on the side surface of the poly 3i pattern, and this side wall is electrically connected to the poly Si pattern 12 at the portion where the side oxide film is removed.

Poly 5i1 deposited between poly Si patterns 11 and 12
5, since both patterns are provided close to each other,
It will undergo a process similar to filling the trenches with poly-Si and etch banking, and the poly 5iJij will remain in the same way as the trenches were filled.

The above are the processing steps of the present invention.
This is effective when forming one side of the OS inverter on a poly-Si sidewall. This CMOS device was invented by the same inventor as the present invention, and a patent application was filed on the same day as the present application, and has the structure shown in FIG.

FIG. 2 is a schematic plan view and a sectional view showing an application example of the present invention. 20 is a Si substrate, which has two S/D regions 22, a gate electrode 21, and an underlying gate insulating film 25.
A channel transistor is configured.

On the other hand, in the n-channel transistor, poly-Si is deposited surrounding the side surfaces of the gate electrode 21, which is a common gate.
It is formed on the sidewall, and 23 is the SZDg area,
24 is a channel region. Although the length of the channel region is exaggerated in the figure, it is actually set to the required length.

The oxide film provided between the gate electrodes when forming the poly-Si sidewall is the gate insulating film 26.

The drains of both transistors are connected through an AI layer 27.

If such a structure is adopted, the channel length of the n-channel transistor is determined by the dimensions and shape of the gate electrode, so it is easy to ensure the necessary length.

In this device, in order to provide wiring to the S/D ti region of the poly-Si transistor, it is necessary to connect the S/D region and the poly-Si pattern 28 prepared in advance with a conductor. The method of the invention is used here. That is, at the same time as the insulated sidewall around the gate electrode, a sidewall without an insulating film is formed on the side surface of the poly-Si pattern 28, and the MO formed on the wall is again formed.
S/D tiI region 23 of S transistor and poly-Si
Connect pattern 28.

In this application example, the MOS transistor is formed on the sidewall, so its impurity concentration is relatively low (the connection part may have high resistance, but the MOS transistor)
This problem can be solved by diffusing impurities into the /D region also into the connection portion.

〔Effect of the invention〕

As explained above, according to the method of the present invention, a poly-Si sidewall can be electrically connected to another poly-Si pattern.

[Brief explanation of the drawing]

Fig. 1 is a schematic diagram showing the process of connecting a poly-Si pattern and a sidewall. Fig. 2 is a schematic plan view and cross-sectional view showing an application example of the present invention. Fig. 3 is a schematic cross-section showing an example of using a known sidewall. It is a diagram. In the figure, 10 is the substrate, 11.12 is polySt. 13, 14 are SiO2, 15 is photoresist, 16 is poly 5i1, 20 is Si substrate, 21 is gate electrode, 22, 23 is S/D wI region, 24 is channel region, 25, 26 is gate insulating film, 27 is Aj wiring, 28 is a poly-Si pattern, 30 is a Si-based pattern, 31 is an S/D region, 32 is a gate electrode, and 33 is a side wall.

Claims (1)

[Claims] An insulating film is selectively deposited on the side surfaces of a first polycrystalline silicon layer existing on the surface of a semiconductor substrate, and a second polycrystalline silicon layer is formed on the entire surface of the substrate by a chemical vapor reaction method. After being deposited,
The second polycrystalline silicon layer is etched by an anisotropic dry etching method, and the second polycrystalline silicon layer electrically connected to the first polycrystalline silicon layer is etched by the first polycrystalline silicon layer. 1. A method of manufacturing a semiconductor device, comprising forming a crystalline silicon layer on a side surface thereof.