JPH03219677A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enable a source/drain contact to be formed easily by providing a recessed part on a semiconductor substrate, a gate electrode with a round lower-part peripheral edge at the recessed part, and then a source and a drain regions on the surface of the semiconductor substrate. CONSTITUTION:An opening is formed by coating an Si3N4 film 12 on an Si substrate 11. The Si substrate 11 is subjected to anisotropic dry etching with the Si3N4 film 12 as an etching mask. Then, with the Si3N4 film 12 as an etching mask, the Si substrate 11 is further subjected to wet etching, thus forming a recessed part whose bottom part is no flat. After that, the Si3N4 film 12 which is used as an etching mask is eliminated and an SiO2 film 13 for a gate is formed by thermal oxidation. Then, a poly Si film 14 and a tungsten polycide is laminated, patterning is made, and then a gate electrode is formed within the previously formed recess. After that, after a source/drain diffusion layer is formed by ion-implantation, an MOS semiconductor integrated circuit is formed.

Description

DETAILED DESCRIPTION OF THE INVENTION (Summary) The present invention relates to semiconductor memory cells that are becoming increasingly highly integrated.

A recess is provided on the semiconductor substrate for the purpose of miniaturizing the cell without reducing the channel length and effectively forming the source/drain electrodes. A rounded gate electrode is provided, and source and drain regions (4) are provided on the surface of the semiconductor substrate.

[Industrial application field]

The present invention relates to highly integrated (semiconductor memory cells).

In recent years, semiconductor memory cells have been steadily becoming more highly integrated. In order to achieve higher levels of integration, it is necessary to reduce device design rules, but major issues are how to design memory storage capacitors and how to design devices without reducing channel length. .

Furthermore, with miniaturization, it has become difficult to form source/drain contact electrodes.

[Conventional technology]

The most common technique in conventional field effect transistors is to form source and drain contact regions and channel regions in the same plane.

For this reason, many efforts have been made to form contacts for the focus lines as miniaturization progresses. Furthermore, as devices become smaller, short channel effects can no longer be ignored.

On the other hand, even when the source/drain region is different from the channel region, when forming the gate oxide film.

and a drop in breakdown voltage due to stress concentration during gate electrode formation, and electric field concentration on the edges due to the shape of the gate electrode.
Also, the withstand voltage decreased due to stress concentration, etc.

[Problem to be solved by the invention]

As described above, with the miniaturization of devices, it has become difficult to fill conductor holes in bit lines, and the single channel effect has caused a decrease in device reliability.

Furthermore, if the contact region and the channel region are formed in non-coplanar planes, the reliability of the gate oxide film will be seriously impaired due to the formation of a non-uniform oxide film and stress concentration.

[Means to solve the problem]

FIG. 1 is a diagram explaining the principle of the present invention.

In the figure, 1. is a semiconductor substrate, 2 is a recess, 3 is a gate electrode, 4 is a source, 5 is a drain, and 6 is a gate Sin!
7 is an element isolation 5i (h film), 8 is a glabellar insulating film, 9 is a source electrode, and 10 is a drain electrode.

In view of two or more points, the present invention forms the contact regions of the source 4 and drain 5 on a different surface from the channel region of the gate, as shown in FIG.

The channel area should be given a gentle slope.

That is, a recess 2 is provided on the semiconductor substrate l, and a gate electrode 3 having a rounded lower peripheral edge is provided in the recess 2 to prevent concentration of electric fields and stress.

Moreover, the object is achieved by providing source and drain regions 4.5 on the surface of the semiconductor substrate.

[Operation] By means of the present invention, the apparent length can be reduced without reducing the gate execution length.

Further, the bit line can be easily contacted, and a highly reliable gate oxide film and gate electrode can be realized.

〔Example〕

FIG. 2 is a schematic cross-sectional view of the process order of the first embodiment of the present invention, FIG. 3 is a schematic cross-sectional view of the process order of the second embodiment of the present invention, and FIG.
The figure is a schematic sectional view of the process order of the third embodiment of the present invention.

In the figure, 11 is a Si substrate, 12 is a 5iJ4 film, and 13 is a Si substrate.
is a 5i02 film, 14 is a poly-Si film, 15 is a 12 film,
16 is a source/drain diffusion layer, 17 is an interlayer 5iO
z film, 18 is an epitaxial layer.

The first embodiment will be explained with reference to FIG.

As shown in FIG. 2(a), CVD was performed on the St substrate 11.
A 5iJa film 12 was coated to a thickness of i,ooo by a method.

Patterning is performed to form 4,000 openings.

As shown in FIG. 2(b), using the Si, N, and film 12 as an etching mask, the St substrate 11 is anisotropically dry etched to a depth of 3,000 mm.

Next, as shown in FIG. 2(C), a Si3N4 film 1 is formed.
2 as an etching mask, add S1 base Fi11.

2. Perform isotropic wet etching for 2,000 people to form a recess with a non-flat bottom.

Thereafter, as shown in FIG. 2(d), the 5t3N film 12 used as an etching mask is removed, and a SiO□ film 13 for the gate is formed to a thickness of 100 nm by thermal oxidation.

Subsequently, as shown in FIG. 2(e), a poly-Si film 14 is laminated to a thickness of 2,000 layers and a tungsten polycide layer is laminated to a thickness of 2,000 layers, and patterned to fill the previously formed recesses. , forming a gate electrode.

Thereafter, as shown in FIG. 2(f), source/drain diffusion layers are formed by ion implantation, and then an MO3 semiconductor integrated circuit shown in FIG. 2(g) is formed by a normal process.

As described above, by forming the gate to be buried below the source and drain regions, the apparent length can be reduced without reducing the gate effective length.

Further, in terms of device formation, bit line contact can be easily made, and a gate oxide film and gate electrode with high reliability can be realized.

Next, a second embodiment will be explained with reference to FIG.

As shown in FIG. 3(a), the St substrate 11 is made of Si, N
.

Using the film 12 as a mask, it is removed by wet etching or the like to form a 5i02 film 13 for a gate.

Next, as shown in FIG. 3(C), polycide was formed and patterned to form a gate electrode.

Glabella SiO□ film 1 is applied to the entire surface with a thickness of 1 μm by CVD method.
After coating the Si substrate 117, as shown in FIG. 3(d), the Si substrate 117 is left only on the side walls of the gate electrode using the RIB method.

Use as a side wall.

Finally, as shown in FIG. 3(e), a selective epitaxial layer 18 is grown on the exposed surface of St on the St substrate 11, and source/drain diffusion regions are formed by ion implantation. By creating a step between the region and the channel region and forming the gate buried below the source and drain regions, the apparent length can be reduced without reducing the execution length of the two gates. .

After this, an MO3 semiconductor integrated circuit is formed by a normal process.

Furthermore, a third embodiment will be explained with reference to FIG.

As shown in FIG. 4(a), ions are implanted into the Si substrate 11 to form source/drain diffusion layers in advance.

As shown in FIG. 4(b), anisotropic etching is performed using the St, N4 film 12 as a mask.

Subsequently, as shown in FIG. 4(c), a channel forming region of the concave portion is formed by isotropic etching such as wet etching.

As shown in FIG. 4(d), after removing the Si3N film 12, oxide Wa 13 for the gate is formed to a thickness of 100 nm.

As shown in FIG. 4(e), finally, polycide is formed and gate electrodes are formed in the recesses by patterning, after which an MO3 integrated circuit is formed by a conventional wafer process.

As described above, the structure is the same as that of the first embodiment, and by forming the gate in a buried form from the source and drain regions, the apparent length can be reduced without reducing the gate effective length. Furthermore, by making the lower part of the 9 gates have a rounded shape instead of an acute angle, it is possible to eliminate electric field and stress concentration.

(Effects of the Invention) As explained above, according to the present invention, the formation of source/drain contacts, which is a problem when producing high-density devices, is facilitated, and the apparent dimensions are lower than the actual dimensions. Since the channel length can be increased, the short channel effect can be prevented.

In addition, it is possible to eliminate stress concentration caused by differences in the electric field and elastic constant concentrated at the edge of the gate electrode, which greatly contributes to improving the quality of the device.

[Brief explanation of drawings]

FIG. 1 is a diagram explaining the principle of the present invention. FIG. 2 is a schematic sectional view of the process order of the first embodiment of the present invention. FIG. 3 is a schematic sectional view of a second embodiment of the present invention in the order of steps. FIG. 4 is a schematic sectional view of the process order of the third embodiment of the present invention. In fig. 1 is a semiconductor substrate, 2 is a recess. 3 is the gate electrode, 4 is the source. 5 is a drain, 6 is a gate oxide film 7 is an element isolation oxide film, and 8 is an insulating film between the eyebrows. 9 is a source electrode, 10 is a drain electrode. 11 is a Si substrate, and 12 is a 5iJ4 film. 13 is an SfO□ film, and 14 is a polySt film. 15 is a WSi2 film 16 is a source/drain diffusion layer. 17 is an interlayer Sin film. 18 is the first large example of the epitaxial layer Kikomei, which is a folded surface diagram of the first large example. Fig. 454-

Claims (1)

[Claims] A recess (2) is provided on the semiconductor substrate (1), a gate electrode (3) having a rounded lower periphery is provided in the recess (2) to prevent concentration of electric fields and stress, and A source (4) and a drain (
5) A semiconductor device comprising a region.