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JPS63100817A - Snubber circuit for gate turn-off thyristor - Google Patents

Snubber circuit for gate turn-off thyristor

Info

Publication number
JPS63100817A
JPS63100817A JP24527286A JP24527286A JPS63100817A JP S63100817 A JPS63100817 A JP S63100817A JP 24527286 A JP24527286 A JP 24527286A JP 24527286 A JP24527286 A JP 24527286A JP S63100817 A JPS63100817 A JP S63100817A
Authority
JP
Japan
Prior art keywords
snubber
snubber circuit
turn
circuit
gtos
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24527286A
Other languages
Japanese (ja)
Inventor
Katsunori Senda
千田 克則
Shigeo Tomita
富田 滋男
Kenji Koga
健司 古賀
Fumio Goto
後藤 文雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP24527286A priority Critical patent/JPS63100817A/en
Publication of JPS63100817A publication Critical patent/JPS63100817A/en
Pending legal-status Critical Current

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  • Thyristor Switches And Gates (AREA)

Abstract

PURPOSE:To balance currents flowing to GTOs at turn-off by using two gate turn-off thyristors GTOs in pairs and arranging a turn-off snubber circuit at the middle of both GTOs. CONSTITUTION:The titled circuit consists of two GTO modules connected in parallel. Anodes and cathodes of the GTO modules are connected by copper bus bars 2a, 2b and the snubber circuit, especially a snubber diode 4 and a snubber capacitor 5 in the turn-off snubber circuit are provided between the bus bars 2a and 2b so as to be placed summetrically (inbetween both modules) with respect to a line segment A-A. Thus, the wiring impedance of the snubber circuit is equal, and the currents iS1, iS2 flowing from both GTOs to the snubber circuit through commutation are balanced, then anode currents iA1, iA2 are also balanced and the locus comprising the anode current iA and the anode-cathode voltage VAK is kept.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はゲートターンオフサイリスタ(以下GTOと略
記)のスナバ回路に係り、特に2個のGTOを直接並列
接続して動作させる時、複数化するスナバ回路を簡略化
し、ターンオフ動作の改善に好適なスナバ回路に関する
[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a snubber circuit for a gate turn-off thyristor (hereinafter abbreviated as GTO), and in particular, when two GTOs are directly connected in parallel and operated, the snubber circuit is The present invention relates to a snubber circuit suitable for simplifying the snubber circuit and improving turn-off operation.

〔従来の技術〕[Conventional technology]

従来の2個のGTOを直接並列接続した時のスナバ回路
の配置図を第3図に、又回路図を第4図に示す。
A layout diagram of a snubber circuit when two conventional GTOs are directly connected in parallel is shown in FIG. 3, and a circuit diagram is shown in FIG. 4.

第3図はインバータ1アーム分の構成で、各GTOモジ
ュール1にスナバ回路が各々取付けられているものであ
る。スナバ回路は、有極性スナバ回路で、スナバ抵抗3
.スナバダイオード4゜スナバコンデンサ5から成って
いる。スナバ抵抗3、スナバコンデンサ5はターンオン
用、スナバダイオード4.スナバコンデンサ5はターン
オフ用のスナバ回路を構成する。
FIG. 3 shows a configuration for one inverter arm, in which a snubber circuit is attached to each GTO module 1. The snubber circuit is a polar snubber circuit with three snubber resistors.
.. It consists of a snubber diode and a 4° snubber capacitor 5. Snubber resistor 3, snubber capacitor 5 is for turn-on, snubber diode 4. Snubber capacitor 5 constitutes a turn-off snubber circuit.

尚、第3図で2a、2bは、アノード、カソードのブス
バーである。
In FIG. 3, 2a and 2b are bus bars for the anode and cathode.

このようなものは、アイビーイージー・トーキヨウ マ
ーチ27−31.1983.ボリューム1 インターナ
ショナルパワー エレクトロニクス(IPEC−Tok
yo March 27−31.1983 Vofl 
、!INTERNATIONAL POWERELEC
TRONIC3)の第54頁がら第64頁に示されてい
る。
This kind of thing is Ivy Easy Tokyo March 27-31.1983. Volume 1 International Power Electronics (IPEC-Tok
yo March 27-31.1983 Vofl
,! INTERNATIONAL POWERELEC
TRONIC3), pages 54 to 64.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上記従来のGTOの直接並列接続時のスナバ回路配線及
び位置では、各々のスナバ回路に配線インピーダンスの
アンバランスが生じる。又、各々スナバダイオード4.
スナバコンデンサ5の内部インピーダンスが異なってく
る為、GTOのターンオフ時、第5図(a)〜(C)に
示す様に、アノード電流i^1.i^2の降下期間時に
スナバ回路へ転流するスナバfri流ist、 isx
がばらつく。
With the snubber circuit wiring and position when the conventional GTOs are directly connected in parallel, an imbalance of wiring impedance occurs in each snubber circuit. Also, each snubber diode 4.
Since the internal impedance of the snubber capacitor 5 differs, when the GTO is turned off, the anode current i^1. The snubber current is commutated to the snubber circuit during the falling period of i^2, isx
varies.

即ち、L(isz側) X d ist/ d t =
 L(isz側)Xdisz/dt=一定であるため、
1、がばらつくことによって、dis/dtがばらつき
、スナバ電流xsi、 xszがばらついていた。従っ
て、iAl。
That is, L (isz side) X d ist/d t =
Since L (isz side) Xdisz/dt=constant,
1, dis/dt varied, and the snubber currents xsi and xsz also varied. Therefore, iAl.

i^2が降下期間時にばらつくこととなり、iAlと■
^にのローカスが、i^2とvAKのローカスより外に
脹らみ、ASO(安全動作領域)外破壊或いは素子劣化
に至る問題があった。
i^2 will vary during the falling period, and iAl and ■
There was a problem that the locus of ^ swelled outward from the locus of i^2 and vAK, leading to destruction outside the ASO (safe operating area) or element deterioration.

本発明の目的は、上述の問題を排除し、ターンオフ時に
GTOに流れる電流をバランスさせることのできるGT
Oのスナバ回路を伜供することにある。
It is an object of the present invention to eliminate the above-mentioned problems and to provide a GT
The purpose is to provide an O snubber circuit.

〔問題点を解決するための手段〕[Means for solving problems]

前述の問題を解決する為には、正確にスナバ回路配線イ
ンピーダンス及びスナバダイオード7゜スナバコンデン
サ9の内部インピーダンスを揃えるのも一つの方法とさ
れるが、位置合わせ及び受動素子の選別等に時間を浪費
するという欠点がある。
In order to solve the above-mentioned problem, one method is to accurately align the snubber circuit wiring impedance and the internal impedance of the snubber diode 7° and snubber capacitor 9, but it takes time to align and select passive elements. It has the disadvantage of being wasted.

それゆえ、上記目的は、スナバ回路を単一化し、特にオ
フスナバ回路(スナバダイオードとスナバコンデンサの
パス)を2個直接並列接続しているGTOlに対して左
右対称な位置、すなわち中間に据えることで解決される
Therefore, the above purpose is to unify the snubber circuit, and in particular to place the off-snubber circuit (path of the snubber diode and snubber capacitor) in a symmetrical position, that is, in the middle, with respect to the GTOL, which has two directly connected in parallel. resolved.

〔作用〕[Effect]

第3図の配線においては、第5図の如くの電流波形とな
ることから、スナバ回路を単一とし1両GTOに対して
共用とし、対称な位置におけば2スナバ回路時に発生す
るインピーダンス特にオフスナバ回路のずれをなくすこ
とができる。従って、GT○降下期間時、スナバ回路へ
転流するスナバ電流i sz 、 i szの電流アン
バランスが低減でき、AS○近傍での動作を抑え、GT
Oの劣化或いは破壊を防ぐことができる。
In the wiring shown in Fig. 3, the current waveform is as shown in Fig. 5, so the snubber circuit is single and shared for one GTO, and if it is placed in a symmetrical position, the impedance that occurs when the two snubber circuits are Misalignment of the off-snubber circuit can be eliminated. Therefore, during the GT○ drop period, the current imbalance of the snubber currents i sz and i sz commutated to the snubber circuit can be reduced, the operation near AS○ can be suppressed, and the GT
Deterioration or destruction of O can be prevented.

一方、ターンオン用スナバ回路は、GTOターンオン時
のアノード電流上昇率di/dtを抑える為、通常はス
ナバ抵抗の配線を長くすることが多く(di/dtが緩
く、ターンオン電流は、それほどアンバランスしない)
、ターンオフ用スナバ回路の嗜に、両GTOに対して対
称な位置、すなわち、両GTOの中間に置かなくて良い
On the other hand, in the turn-on snubber circuit, in order to suppress the anode current increase rate di/dt at GTO turn-on, the wiring of the snubber resistor is usually made long (di/dt is loose, and the turn-on current is not so unbalanced). )
The turn-off snubber circuit does not need to be placed at a symmetrical position with respect to both GTOs, that is, in the middle between both GTOs.

〔実用例〕[Practical example]

以下、本発明の一実施例を第1図において説明する。第
2図は、第1図の等価回路である。
An embodiment of the present invention will be described below with reference to FIG. FIG. 2 is an equivalent circuit of FIG. 1.

第1図は、GTOモジュールを2個直接並列接続したも
のである。GTOモジュール1は、銅ブスバー2a、2
bによって、各モジュールのアノード及びカソードが接
続され、スナバ回路、特にターンオフ用スナバ回路のス
ナバダイオード4とスナバコンデンサ5は、線分A −
Aに対して対称な位置(両モジュールの中心)に置かれ
る様、ブスバー2a、2b間に設けられている。
FIG. 1 shows two GTO modules directly connected in parallel. The GTO module 1 includes copper busbars 2a, 2
b connects the anode and cathode of each module, and the snubber diode 4 and snubber capacitor 5 of the snubber circuit, especially the turn-off snubber circuit, are connected by the line segment A −
It is provided between the bus bars 2a and 2b so as to be placed at a symmetrical position with respect to A (center of both modules).

このため、スナバ回路における、配線インピーダンスは
等しくなり、スナバ回路に両GTOから転流して流れる
電流isx、 iszはバランスし、従って、アノード
電流iAz、 ’hAxもバランスし、i^とV^にの
ローカスを外れなくなる。
Therefore, the wiring impedance in the snubber circuit becomes equal, and the currents isx and isz commutated from both GTOs to the snubber circuit are balanced.Therefore, the anode currents iAz and 'hAx are also balanced, and the difference between i^ and V^ is Can't leave the locus.

GTOが偶数個並列接続される時、2個のGTOを単位
として、各GTO単位の中心に各々スナバ回路を配置す
る。
When an even number of GTOs are connected in parallel, a snubber circuit is placed at the center of each GTO unit, with two GTOs as a unit.

尚、第1図、第2図ではフライホイールダイオードにつ
いて触れていないけれども、フライホイールダイオード
が各GTOに逆並列接続されていても良い、ターンオフ
時には、フライホイールダイオードには電流は流れてい
ないから、スナバ回路はフライホイールダイオードに対
しては、自由な位置に配置してかまわない、逆に云えば
、フライホイールダイオードが1個のパンケージ内にG
TOと共に封止される時、スナバ回路が中心にくる様な
GTOの配置に注意すればよく、フライホイールダイオ
ードは、パッケージ内の任意な位置のマウントが許され
る。
Although the flywheel diode is not mentioned in Figures 1 and 2, the flywheel diode may be connected in antiparallel to each GTO, since no current flows through the flywheel diode at turn-off. The snubber circuit can be placed in any position relative to the flywheel diode; conversely, the snubber circuit can be placed in any position relative to the flywheel diode.
When sealed with the TO, care should be taken to position the GTO so that the snubber circuit is centered, and the flywheel diode can be mounted anywhere within the package.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、2個のGTOモジュールによる直接並
列接続でインバータ等の装置を製作する場合、特にター
ンオフ用スナバ回路(スナバダイオードとスナバコンデ
ンサのパス)を単一化し、両GTOモジュールの対称な
位置、すなわち中間に据えることによって、確実にGT
Oターンオフ時の降下期間の電流アンバランスを低く抑
え、ASO領域近傍スイッチング動作を防ぐと共に、ス
ナバ回路単一化による装置のコンパクト化が達成できる
According to the present invention, when manufacturing a device such as an inverter by directly connecting two GTO modules in parallel, the turn-off snubber circuit (pass between the snubber diode and the snubber capacitor) is unified, and the symmetrical connection of both GTO modules is performed. position, that is, in the middle, to ensure GT
It is possible to suppress the current imbalance during the drop period at O turn-off, prevent switching operation near the ASO region, and make the device more compact by integrating the snubber circuit.

又、本方式では、有極性スナバ回路を欲するス、イヤチ
ング素子の2個直接並列接続時にも適用可能である。
Furthermore, this method can also be applied when two earring elements are directly connected in parallel in a case where a polar snubber circuit is desired.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示すGTOの斜視図、第2
図は第1図の等価回路図、第3図は従来の直接並列接続
の一例を示すGTOの斜視図、第4図は第3図の等価回
路図、第5図(a)〜(c)は第3図での各都電圧、電
流波形(ターンオフ時)を示す図である。 1・・・GTOモジュール、2・・・銅ブスバー、3・
・・スナバ抵抗、4・・・スナバダイオード、5・・・
スナバコンデンサ、6・・・GTO17・・・スナバダ
イオード、8・・・スナバ抵抗、9・・・スナバコンデ
ンサ。
Fig. 1 is a perspective view of a GTO showing one embodiment of the present invention;
The figure is an equivalent circuit diagram of Figure 1, Figure 3 is a perspective view of a GTO showing an example of conventional direct parallel connection, Figure 4 is an equivalent circuit diagram of Figure 3, and Figures 5 (a) to (c). is a diagram showing voltage and current waveforms (at turn-off) at each point in FIG. 3. 1...GTO module, 2...copper busbar, 3.
...Snubber resistor, 4...Snubber diode, 5...
Snubber capacitor, 6... GTO17... Snubber diode, 8... Snubber resistor, 9... Snubber capacitor.

Claims (1)

【特許請求の範囲】 1、ゲートターンオフサイリスタが並列接続されるもの
において、2個のゲートターンオフサイリスタを1組と
して、両ゲートターンオフサイリスタの中央に1個のタ
ーンオフ用スナバ回路が配置されることを特徴とするゲ
ートターンオフサイリスタのスナバ回路。 2、上記スナバ回路は、2個のゲートターンオフサイリ
スタを並列接続するブスバーに接続されていることを特
徴とする特許請求の範囲第1項のゲートターンオフサイ
リスタのスナバ回路。
[Claims] 1. In a device in which gate turn-off thyristors are connected in parallel, two gate turn-off thyristors are set as one set, and one turn-off snubber circuit is arranged in the center of both gate turn-off thyristors. Features a gate turn-off thyristor snubber circuit. 2. The snubber circuit for a gate turn-off thyristor according to claim 1, wherein the snubber circuit is connected to a bus bar connecting two gate turn-off thyristors in parallel.
JP24527286A 1986-10-17 1986-10-17 Snubber circuit for gate turn-off thyristor Pending JPS63100817A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24527286A JPS63100817A (en) 1986-10-17 1986-10-17 Snubber circuit for gate turn-off thyristor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24527286A JPS63100817A (en) 1986-10-17 1986-10-17 Snubber circuit for gate turn-off thyristor

Publications (1)

Publication Number Publication Date
JPS63100817A true JPS63100817A (en) 1988-05-02

Family

ID=17131210

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24527286A Pending JPS63100817A (en) 1986-10-17 1986-10-17 Snubber circuit for gate turn-off thyristor

Country Status (1)

Country Link
JP (1) JPS63100817A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208495A (en) * 1991-12-30 1993-05-04 Ferraz Static power switch incorporating semi-conductor

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208495A (en) * 1991-12-30 1993-05-04 Ferraz Static power switch incorporating semi-conductor

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