JPS6297073A - Image display device memory address conversion method - Google Patents

Abstract

PURPOSE:To attain various types of displays of pictures by converting the output of an address counter into a picture memory address by a memory address converting part having a bit processing means and giving access to a picture memory. CONSTITUTION:The value of an address counter 6 is delivered as a display memory address 60 to instruct an address of a display memory 3'. While the value of the counter 6 is also delivered to a memory address converting part 7. The part 7 selects each bit selecting part by the instruction of a mode instructing part 76 and converts it into an address of a display mode to deliver it as a picture memory address 80. Therefore both addresses 60 and 80 are instructed by the output of the value of the counter 6. Thus the data on the address of a picture memory 1 is read out and displayed on the screen of a display 4 corresponding to the address of the memory 3'.

Description

[Detailed Description of the Invention] [Summary] A memory address conversion method for an image display device, which converts the output of an address counter (display memory address) into an image memory address by a memory address conversion unit having bit processing means, To access the contents of an image memory with a simple circuit configuration and to enable various display expressions.

[Industrial application field]

The present invention relates to a method for converting the output of an address counter into an address of an image memory in order to display the contents of the image memory of an image display device.

An image to be displayed on an image display device is stored as digital data in an image memory, and data of contents to be displayed is transferred to a display memory (refresh memory) corresponding to a pixel of a display screen and displayed on a display.

However, image memory typically has a larger memory capacity than display memory and stores more image information.

Therefore, in order to display the image, one part of the image memory is
In order to transfer the image to the display memory, the display memory address is converted to a corresponding image memory address and the image memory is accessed.

The display memory has a memory capacity equivalent to one display screen of the display, and the contents of the memory are displayed as they are.

Therefore, segment display that displays part of the contents of the image memory, increment display that displays the contents of the image memory with skipped lines, and segment display that displays part of the contents of the image memory,
When executing functions such as magnification display to enlarge the area, and scroll display function to display both images shifted, the image memory address is changed to the display memory address by address operation, that is, address conversion including these functions is performed. access data.

Furthermore, in order to display a changing image, it is necessary to quickly transfer the display contents from the image memory by quick address conversion.

Therefore, there is a need for a system that can perform memory address conversion with a simple circuit configuration.

[Conventional technology]

FIG. 12 shows a memory address conversion method of a conventional image display device.

Address conversion in conventional image display devices is performed line by line using a line counter 2 for one line of the image memory 1.

That is, when displaying one screen worth of display, first reset the line counter 2, then start counting, and when the counted value from the counting start point reaches one line of the display memory 3,
Display that one line of data on the display 4, then reset the line counter 2, and
The value for the row is added as an offset value to the line counter 2 by an adder 5, and then counting for the next row is started.

Further, when scrolling is performed, it is necessary to add the value for scrolling as an offset when the display of one screen is first reset.

Control of each of the circuits described above is performed by a control section 10 composed of, for example, a microcomputer.

[Problem that the invention seeks to solve]

In this conventional system, a line counter 2 for one line of the image memory 1 is provided, and all operations of the system are performed through the intervention of the control section 10.

For example, the count up of the line counter 2 is also controlled by the control unit 10.
instructions are required.

Therefore, if an attempt is made to enhance display functions, more complicated control is required, making it impossible to quickly display images.

That is, if an attempt is made to add not only segment display for displaying a portion of the image memory, but also other display functions, more time will be required for address conversion operations, and control will become complicated.

The present invention was created in view of the above points, and an object of the present invention is to provide an address conversion method for an image display device that can realize various display functions for displaying images with simple control and circuit configuration. It is an object.

[Means for Solving the Problems] FIG. 1 is a block diagram of an embodiment of a memory address conversion method for an image display device of the present invention, and FIG. 2 shows its memory address conversion section.

1 is an image memory, 3'' is a display memory, and 6 is an address counter, which has the same maximum value as the maximum address value of the display memory 3''.

Reference numeral 7 designates an address memory conversion unit that selectively controls an input register 70, a bit value setting unit 71 that performs bit processing for address code conversion, a shift processing unit 72, an addition processing unit 73, an offset register 74, and these bit manipulation means. a processing control section 75 that is used to realize various display functions, a mode instruction section 76 that instructs the display mode, and an output register 77.
60 is a display memory address, and 80 is an image memory address.

Output value of address counter 6 is displayed memory address 60
The circuit is configured to specify the image memory address 80 via the memory address converter 7.

[Effect]

The value of the address counter 6 is output as a display memory address 60, indicating the address of the display memory 3', while the same counter value is output to the memory address converter 7.

Based on instructions from the mode instruction section 76, the memory address conversion section 7 selectively selects each bit processing section as shown in FIG. 3, converts it into a display mode address, and outputs it as an image memory address 80. .

Therefore, by outputting the value of the address counter 6, the display memory address 60 and the image memory address 80 are designated, and the data at the address in the image memory 1 is read out, and the data on the display 4 corresponding to the address in the display memory 3' is read out. displayed on the screen.

Therefore, as the address counter 6 sequentially counts up, the data in the image memory 1 is read out to the display memory 3' at the corresponding address and displayed on the screen of the display 4.

〔Example〕

Hereinafter, the memory address conversion method of the image display device of the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of a memory address conversion section, FIG. 3 is an explanatory diagram of the relationship between display modes and processing means, and FIG. 4 is a flowchart of memory address conversion.

In order to facilitate understanding of the explanation of the memory address conversion method of the image display device of the present invention, the display memory 3 of the image display device stores 512×512 pixel data, and the image memory 1 stores 1024×1024 pixel data. Explain when to do so.

An address is assigned to each pixel, and FIG. 5 is a bitmap showing the address assignment of each memory.

In the figure, addresses are expressed in hexadecimal codes with 4 bytes as a unit.

That is, the address of the first row of the display memory 3'' is ro O
000J to rooIFFJ, line 512 is r3FEO
OJ to r3FFFFJ.

Further, the image memory 1 is divided into four segments of 512×512 bits: ①, ②, ②, ②.

Furthermore, a display memory 3° for storing each segment is shown in FIG.
The correspondence between the address of the image memory 1 and the address of the image memory 1 on a row-by-row basis is shown.

That is, the addresses ro 0000J to ro of the image memory 1
Addresses ro 0000J to 001FFJ of the display memory 3' displaying 01FFJ and segment (2) correspond.

Also, address ro O200J~r00 of image memory 1
3FFJ and the addresses roOO00J to rooIFF of the display memory 3' that display segment (2) correspond.

The last line of display memory 3' r3FEOOJ ~ "3FFFF
J is segment ■ display memory 3° is image memory 1 r
7FcOOJ to r7FDFFJ, and the display memory 3' of segment (2) corresponds to r7FEOOJ to r7FFFFJ.

Similarly, the display memory 3' that displays segments ■ and ■ is
The same correspondence as above is applied to r80000J to rFFFFFFJ of image memory 1.

Next, various display functions, that is, address conversion operations for designated modes will be explained.

(1) Segment mode (Figure 7) The output value of the address counter 6 is input to the input register 70 of the memory address converter 7 (Figure 7(a)), and the mode instruction unit 76 selects the segment mode in this case. The output register 77 is set to "0" for bits 9 and 19 by the bit value setting section 71, and bits O to 8 of the input register 70 are transferred to bits 0 to 8 of the output register 77, and the shift processing section 72, bits 9 to 17 of input register 70 are shifted and transferred to bits 10 to 18 of output register 77 (FIG. 7(b)).

The 20-bit address created in this way is output from the output register 77 as the image memory address 80.

In the case of displaying segments ■, ■, ■, the bit value specifying unit 24 sets bit 9 to rlJ, rOJ, rlJ and bit 19 to rOJ, rlJ, respectively, in the initial setting of the bits.
, rlJ, and bits 8 to 17 of the input register 70 are set to bits 0 to 8 of the input register 77, respectively. Transferred to bits 10-18.

(2) Increce mode (FIG. 8) In the case of increment mode in which lines in the image memory 1 are skipped and displayed one by one, the processing control section 75 selects the bit value selection section 71 and the shift processing section 72, Output register 77
Set bits 9 and 19 according to the segment to be displayed in the same way as in the segment mode, and set bit O.
~8 are transferred as they are between codes, bits 9 to 16 are transferred to bits 11 to 18, bit 17 is transferred to bit 10 (Figure 8(a) is the input register code, 8(b) is the input register code,
(C1゜fd), (e) The figure shows the output register code for converting segments ■, ■, ■).

(3) Scroll mode (Fig. 9) When displaying in a scroll mode in which the display is performed at a shifted position, the contents stored in the offset register 74 are used, and in the line scroll mode, the scroll amount is specified in the upper lO bit of the offset register 74. By adding it to the upper 10 bits of the output register 77, a scroll screen with shifted rows can be obtained (11th (a)
figure).

Furthermore, by adding the contents of the offset register 74 stored in the lower 10 bits to the lower 10 bits of the output register 77, column scrolling can be obtained (first
1C mouth) Figure).

In this manner, the offset register 74 is a 20-bit register in which the row offset value is stored in the upper 10 bits and the column offset value in the lower 10 bits, and is cleared when scroll processing is not performed.

4) Enlargement mode (Fig. 11) For example, to enlarge and display the data of segment 2 of image memory 1, bits 1 to 8 of input register 7o are set to bits O to 7, and bits 10 to 17 are set to bits 9 to 7. By shifting to 16 and specifying bit 8.17 as "0", the double enlargement mode is set (FIG. 11(A)).

Note that Figure (a) shows the input register code, and Figure (b) shows the output register code.

Similarly, specify bits 7.8.16.17 as rOJ, bits 2-8 as bits 0-6, bits 11-17 as 9-
By shifting to 15, the mode becomes 4 times enlarged (Figure 11 (b)).

Furthermore, by designating bits 6 to 8, 15 to 17 as "0" and shifting bits 12 to 17 to focus 9 to 14, an 8x enlargement mode is set (FIG. 11(c)).

As described above, the processing control section 75 of the memory address conversion section 7 selects each bit processing section 71 to 73 based on the contents of the mode instruction section 76, and selects the segment processing, increment processing, scroll processing, etc. of the data processing function. Configure each function of the enlargement process, process the output of the address counter 6 according to the flowchart in FIG. 3, and set the image memory address 80.
and read out the image data.

Furthermore, although the above scrolling involves scrolling the entire image memory, when scrolling within the display screen (inside the viewport) (internal scrolling), the above 10 bits are replaced with 9 bits, as shown in Figure 10. You can add it as .

Then, in the flowchart of FIG. 4, the processing of ■-■ is added to the point X.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to convert memory addresses with an extremely simple circuit configuration, which is extremely useful in practice.

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the memory address conversion method of the image display device of the present invention, Fig. 2 is a block diagram of the memory address conversion section, Fig. 3 is an explanatory diagram of the relationship between display mode and processing means, and Fig. 4 is Memory address conversion flowchart, Figure 5 is a diagram showing memory address allocation, Figure 6 is a diagram explaining memory address correspondence in row units, Figure 7 is a diagram explaining segment mode, Figure 8 is a diagram explaining incremental mode, Figure 9 10 is an explanatory diagram of scroll mode (interior), FIG. 11 is an explanatory diagram of enlargement mode, and FIG. 12 is a block diagram of a conventional example. In the figure, 3' is a display memory, 6 is an address counter, 7 is a memory address conversion section, 71 is a bit value setting section, 72 is a shift processing section, 73 is an addition processing section, 75 is a processing control section, and 76 is a mode instruction 60 is a display memory address, and 80 is an image memory address. Me 1 Mi 7 Dress Tate Otsu Tetsusha p Brown 7-o Wa 7 Shiri @ 2
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Claims (1)

[Claims] An image display device having an image memory at least the same size as the display memory, comprising: an address counter (6) having the same maximum value as the maximum address of the display memory (3'); and a plurality of registers. a bit value setting means (71) for setting a predetermined value in a predetermined bit of a register; a shift processing means (72) for shifting a predetermined bit of a register to a predetermined bit of another register; A memory address conversion unit (7) includes an addition processing unit (73) that adds the contents of other registers, and a processing control unit (75) that selectively combines the units according to instructions from a mode instruction unit (76). The output of the address counter (6) is used as the display memory address (60) and is output to the memory address converter (7), and the output of the memory address converter (7) is used as the image memory address (60). 80), the value of the address counter (6) is converted into an image memory address (80) with control of a display method corresponding to the display memory address (60). Memory address conversion method.