JPS6292056A - Read/write control method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] A processor with an N-bit data bus processes a RAM (Ran) having a data bus of N bits or less, for example, N/2 bits.
This is a read/write control method that allows access to (donAccessMemory).

[Industrial application field]

The present invention relates to an improved read/write control scheme for memory coupled to a processor.

It is desired to implement a readout method (color control method) that facilitates the transfer of data between a processor and a memory having data buses having different numbers of bits.

[Conventional technology]

A conventional example will be explained using figures. FIG. 4 is a block diagram illustrating a conventional example.

Processor 1 is a 16-bit microprocessor. That is, it has a 16-bit data bus, but if a memory with an 8-bit data bus is connected to such a microprocessor, two memories 1 (RAMs) 2 and 3 have a lower byte Bl and an upper byte B2, respectively. In FIG. 2, for example, when processor 1 stores data D'z in register 4, data B+'! of the lower byte of data D is stored. r and sent to the memory 2 via the data bus 5, while the upper byte data B2 is sent to the memory 3 via the data bus 6 and written therein. In addition, Aoi't in the figure
The starting address information A1 to An of the memory 2 is address information, and after the address information A and An are decoded by the decoding circuit 7, the OR gate 8? The signal is then sent to the chip select terminal C8 of the memory 2. Also BNE
is the path enable signal.

[Problem to be Solved by the Invention 3] As described above, in the past, since the method was to divide and store data in a plurality of memories, it was difficult to reduce the size and cost of the device.

[Means for solving the V-tλ point] FIG. 1 is a block diagram of the principle of the present invention. The present invention provides a data writing buffer 15 for the upper byte of the data 20 in a device in which the processing device 1 writes or reads data 20 having a length of N bits into a storage unit 10 in which the block access unit is an N/2 bit unit. and write the lower byte data of data 20 and data 21/
A driver/receiver 16 used for reading, a latch circuit for reading the lower byte data 24 of the data 23, and a shift register 12 that outputs a control signal 26 that causes the buffer 15 and driver/receiver 16 to operate alternately. There is.

[Effect]

When writing data 20 to storage unit 10, shift register 1
2, the upper byte data 21 of the data 20 is written to the entire storage section 15 via the buffer 15, and then the lower byte data 22 is written to the entire storage section via the driver/receiver 16. 15
When data 23 is written to or read by the storage unit 10, the lower byte data 24 that has been read out is temporarily held in the latch circuit 19, and then read out and sent to the driver/receiver 1.
6, along with the upper byte data 25 that has passed through the processing device 1.
Let them take the ta.

〔Example〕

Hereinafter, the present invention will be explained with reference to the drawings. FIG. 2 is a block diagram explaining one embodiment of the present invention, and FIG. 3 is a time chart explaining one embodiment of the present invention.

FIG. 2 shows an example in which a 16-bit processor 1 is connected to a RAM (256 bytes) that can be accessed in bytes. That is, processor 111-j: 16 in register 4
Bit data D. -D+, all writes to the RAM 10 are performed in byte units (8 pits), and also accessed in byte units during reading.

First, the control operation in the case of writing will be explained. Processor 1 sets 16-bit data Do-Dos in register 4, sets write signal MWTC to "0", and outputs address information Ao-A2o. At this time, address information A o −A? to RAM10, and A8 to A. is sent to the decoding section 13. Note that the write signal MWTC is of negative logic.

Furthermore, data transfer signal (signal indicating data transfer direction)
The signal level of DT/R becomes "1", and the activation signal CLK
The pulse generator 11 is started. The clock pass CL thus output drives the shift register 12.

Ready signal aH14 output from shift register 12
As shown in the time chart of FIG. 3g3 (a), at time t, the signal level becomes "0". Therefore, at time t,
The output level of the OR gate 14 becomes "l". The gate terminal G of the buffer 15 becomes "open" and the RAM
The enable terminal E of l0 becomes Enable. As a result, lower byte data Do~D from processor 1
7 is sent to the input end of RAM10. And time j! ,
That is, as shown in FIG. 3(a), when the signal level of the ready signal a from the shift register 12 returns to "1",
Data D6~D? is written to RAM10.

Note that when the signal level of the ready signal a returns to "1", the gate terminal as of the driver/receiver 16 becomes "Ej" and becomes the gate terminal G of the buffer 15.

becomes “closed”. As a result, data D8 to DI4 in the upper byte of register 4 is sent to the input end of RAM10 and written therein.

On the other hand, as shown in FIG. 3(a), the shift register 12 outputs a ready signal (the signal level changes from "1" to rOJ) at time t after a predetermined time T has elapsed. Upon receiving this, processor l sets the write signal MWTC to “1”.
” and completes the write control operation.

Next, the read control operation will be explained using FIGS. 2 and 3 (bl). In FIG. 13 decodes this, RAM
The chip select terminal C8 of l0 is set to Enable.

The low data bus 17 is set to the input mode, and the signal level of the read signal MRDC is changed from "all 11" to "0" (ie, read mode). Furthermore, the pulse generator 11 is all activated by the activation signal CLK, and the shift register 12t is driven by the clock pulse CL generated thereby.

Along with this, the shift register 12 outputs time t! as shown in FIG. 3(b). Ready signal a changes from “1” to “0”
This is applied to the enable terminal E of RAM10. This is it! 11. Data D taken out from RAMl0. -D7 enters the latch circuit 19 and is latched by the ready signal issued from the shift register 12 at time 1s. Then, at time t, the signal level of the ready signal a changes from rOJ to "1" l~, which is RAMl
0 to enable terminal E.

Then, the gate terminal Gs of the driver/receiver 16 becomes "open", and the output signal of the circuit 19 and the data D of the lower byte enter the path 17. -D enters, while bus 18
The upper byte data D8-015 enters through the driver/receiver 16, and is thereby read into the processor 1.

As shown in FIG. 3(b), the signal level of the ready signal changes from "0" to "1" at time t6, and this is transmitted to the READT7.4 child of the processor 1. As a result, the processor 1 terminates the MRDC signal and completes reading of the data Do-D+s.

〔Effect of the invention〕

The present invention has the advantage of facilitating miniaturization and cost reduction of the device.

[Brief explanation of drawings]

Figure 1 is a block diagram of the principle of the present invention. Figure 2 is a block diagram explaining an embodiment of the present invention. Figure 3 is a time chart explaining an embodiment of the present invention. Country 4 describes a conventional example. Bronocle J, In the figure, 1 is the processor, 2, 3.10 is the RAM, 4 Ilt register, 5, 6, 17.18 is the data bus, 7 is the decoding circuit, 8, 9 is the OR gate, 11 is the pulse generator vessel, 1
2 is a shift register, 13 is a decoding section, 14 is an OR gate, 15 is a buffer, 16 is a driver/receiver, 1
9 is a latch circuit, 20.23 is data, 21.24 is lower byte data, 22°-(S 7P-49 month's original seal V) mouth and SO 2 1. J6 Fron 2 Ward 3
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Claims (1)

[Claims] In a device in which a processing device 1 writes or reads data 20 having a length of N bits into a storage unit 10 whose access unit is an N/2 bit unit, data writing of the upper byte of the data 20 is performed. writing buffer 15 and lower byte data of data 20 and data 21/
It includes a driver/receiver 16 used for reading, a latch circuit 19 for reading lower byte data of data 21, and a shift register 12 that outputs a control signal 26 that alternately operates the buffer 15 and driver/receiver 16. When writing 20 to the storage unit 10, shift register 1
2 is activated, the upper byte data 21 of the data 20 is written into the storage section 15 via the buffer 15, and then the driver/driver/
When writing the lower byte data 22 to the storage unit 15 via the receiver 16 or when the storage unit 10 reads the data 23, the read lower byte data 24 is transferred to the latch circuit 15.
9 is temporarily held, and then read out and read by the processing device 1 together with the upper byte data 25 that has passed through the driver/receiver 16.