JPS6290552A - Peak detection circuit - Google Patents

Abstract

PURPOSE:To obtain a peak detection circuit fitted to an IC circuit, by providing logic circuit sending out an output pulse in the timing of the detection output of a zero cross detector, which is sent out immediately after the detection output of a level detector, to a peak pulse generating means. CONSTITUTION:The output pulse of a magnetic head 1 is amplified by an amplifier 2 and, after a noise component was removed by a filter 3, differentiation is performed by a differentiator 4 and a zero cross point is detected by a zero cross detector 5 to output an output pulse C corresponding to a peak position. The output pulses A, A' of the filter 3 are supplied to level detectors 6, 7 to perform level detection. The output pulses A, A' are inverse in polarity to each other and the level detectors 6, 7 respectively perform the detection of positive and negative levels and, when prescribed voltage VT was exceeded, output pulses D, E are outputted. RS-type flip-flop (FF)8 is set by the output pulse D of the level detector 6 and reset by the output pulse of E of the level detector 7. In this way,, the output pulse G of D-type flip-flop (FF)9 is reversed only by the pulse immediately after exceeded voltage VT in the output pulse C-row of the detector 5 and a pulser 10 can output a real peak pulse H.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an improvement of a peak detection circuit suitable for a magnetic recording/reproducing circuit.

〔overview〕

The present invention provides a circuit for detecting that a positive/negative level exceeds a specified value by providing a logic circuit that uses the zero-crossing detector output immediately after the specified value is exceeded as an effective output, thereby omitting a delay circuit. This makes it simple and inexpensive.

[Conventional technology]

FIG. 3 is a block diagram of a conventional peak detection circuit. A peak detection circuit of a conventional magnetic storage device is connected in order to a magnetic head I, an amplifier 2, a filter 3, a differentiator 4 and a zero crossing detector 5, as shown in FIG. Further, the output pulse of the filter 3 is connected to one input of the level detector 6.7, and the specified voltage Va is connected to the other input of the level detector 6.7. The output pulse of the level detector 6.7 is connected to the OR gate 11, and the output pulse of the OR gate 11 is passed through the delay circuit 12 to the AND gate 13.
connected to one input of the The output pulse of the zero crossing detector 5 is connected to the other input of the AND gate 13.

The operation of the conventional circuit shown in FIG. 3 will be explained.

After the output pulse of the magnetic head 1 is amplified to a predetermined level by an amplifier 2 and noise components are removed by a filter 3, a differentiator 4 and a zero crossing detector 5 detect the peak position.

The level detector 6.7 compares the output pulse of the filter 3 with a specified voltage 7, and activates the output when the output pulse of the filter 3 is equal to or higher than the specified voltage VT. When either of the level detectors 6.7 is active, the OR gate 11 becomes active, and after a delay of the delay time of the delay circuit 12, the ant gate (13) becomes active.
The output pulse of the zero-crossing detector 5 is valid only during this active time.

[Problem that the invention seeks to solve]

However, in such a conventional peak detection circuit, a delay circuit 12 is added to correct the delay time difference between the differentiator 4 and zero crossing detector 5 channels and the level detector 6.7 and OR gate 11 channel. Therefore, it is necessary to adjust the delay time due to component variations. Therefore, the conventional peak detection circuit has the drawback of requiring the use of an expensive delay line for the delay circuit and adjusting the delay time, resulting in a significant increase in cost. Additionally, delay lines have the disadvantage of not being compatible with integrated circuits.

The present invention solves the above-mentioned drawbacks and aims to provide a peak detection circuit that does not require expensive delay lines and delay time adjustments and is inexpensive and compatible with integrated circuits.

[Means for solving problems]

The present invention includes a level detector that detects when the positive and negative voltages of an input pulse exceed specified values, a differentiator that differentiates the input pulse, and a zero crossing point of the output pulse of the differentiator. In a peak detection circuit comprising a zero-crossing detector and means for generating a peak pulse from the detection pulse of the zero-crossing detector and the level detector, the means for generating the peak pulse is configured to generate a peak pulse from the detection pulse of the level detector. It is characterized in that it includes a logic circuit that sends out an output pulse at the timing of the detection output of the zero crossing detector that is sent out immediately after the output.

The logic circuit of the present invention includes an RS type flip-flop in which one of the positive and negative detection pulses of a level detector is used as a set input and the other as a reset input, and an output pulse of this RS type flip-flop is used as a data input, and the above-mentioned zero It can be composed of a D-type flip-flop that receives the output pulse of the crossover detector as a clock input, and a pulser that generates a peak pulse using the output pulse of this D-type flip-flop.

[For production]

The present invention uses the detection pulses on both the positive and negative sides of the level detector to
The type flip-flop is set and reset alternately, and the output pulse is held after the voltage on the positive (negative) side of the input pulse exceeds a specified value until the voltage on the negative (positive) side exceeds the specified value. Since the time for the input pulse to pass through the differentiator and zero-crossing detector is longer than the time for the input pulse to pass through the level detector and the RS-type flip-flop, the output pulse of the RS-type flip-flop is input to the data input of the D-type flip-flop. The output pulse of the zero-crossing detector is inputted to the clock input, and the output pulse of the D-type flip-flop is inverted only by the pulse immediately after exceeding a specified value in the output pulse train of the zero-crossing detector. By generating a peak pulse at the time of reversal of the output pulse of the D-type frisopfloop, which is the true peak timing in a balsa, the peak value can be achieved with a circuit constructed using an inexpensive integrated circuit without the need for expensive delay lines or adjustment of delay time. can be detected.

〔Example〕

Embodiments of the present invention will be described with reference to the drawings.

In FIG. 1, the output pulse of the magnetic head 1 is transmitted to the amplifier 2.
The output pulse from the amplifier 2 is amplified to a predetermined level and is connected to the filter 3. The output pulses A, A' from which noise components have been removed from the filter 3 are connected to a differentiator 4, and the output pulse B differentiated from the differentiator 4 is connected to a zero crossing detector 5. Further, the output pulses A and A' of the filter 3 are respectively connected to one input of a level detector 6.7. A specified voltage 7 is connected to the other inputs of the level detectors 6 and 7, respectively.

Here, the feature of the present invention is the peak value detection portion surrounded by a dashed line. That is, when the output pulses A and A' of the filter 3 are equal to or higher than the specified voltage 71, the detection pulse D of the level detector 6 is connected to the set input S of the flip-flop 8, and the detection pulse E of the level detector 7 is Connected to the reset input of flip-flop 8. The output pulse F of the flip-flop 8 is connected to the data input of the D-type flip-flop 9, while the detection pulse C of the zero-crossing detector 5 is connected to the clock input T of the D-type flip-flop 9. The output pulse G of the D-type flip-flop 9 is connected to a pulser 10, which outputs a peak pulse H.

The operation of the peak detection circuit having such a configuration will be explained.

FIG. 2 is a time chart of signals of each part of the peak detection circuit of the present invention. The symbols shown in Figure 2 are the "x" shown in Figure 1.
” indicates the signal at the position of the mark.

1 and 2, the output pulse of the magnetic head 1 is amplified to a predetermined level by an amplifier 2, noise components are removed by a filter 3, and then differentiated by a differentiator 4. A zero crossing point is detected, and an output pulse C corresponding to the peak position is output. Further, the output pulses A and A' of the filter 3 are supplied to a level detector 6.7 for level detection. The output pulse A' of the filter 3 is of opposite polarity to the output pulse A, and the level detector 6.7 is positive;
Each negative level is detected, and output pulses D and E are output when the voltage exceeds the specified voltage V〒.

The flip-flop 8 is set by the output pulse D of the level detector 6 and reset by the output pulse D of the level detector 7. That is, by holding the output of the flip-flop 8 until the level on the positive (negative) side exceeds the specified voltage 7 and the level on the negative (positive) side exceeds the specified voltage VT, the zero crossing detector 5 output pulse C
The output pulse G of the D-type flip-flop 9 can be inverted only by the pulse immediately after exceeding the specified voltage 1 in the column. The balsa 1o outputs a true peak pulse H at the time of inversion of the output pulse of the D-type flip-flop 9, which is the true peak timing.

Considering the delay time, the delay time of the differentiator 4 and zero crossing detector 5 channels is usually larger than the delay time of the level detector 6.7 and flip-flop 8 channel, so that the delay time is smaller than the true peak position. Also, the output of the flip-flop 8 is surely inverted at the previous timing.

〔Effect of the invention〕

As explained above, the present invention has the excellent effect of being able to detect a peak value with an inexpensive circuit made of an integrated circuit without using an expensive delay line or adjusting the delay time. There is.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a peak detection circuit according to an embodiment of the present invention. FIG. 2 is a time chart of signals in each part of the peak detection circuit of the present invention. FIG. 3 is a block diagram of a conventional peak detection circuit. A, A'... Output pulse of filter (3), B...
・Output pulse of differentiator (4), C...zero crossing detector (
5) output pulse, D...output pulse of level detector (6), E...output pulse of level detector (7), F
...Output pulse of RS type flip-flop (8), G
...Output pulse of D type flip-flop (9), H.
... Output pulse of pulser (10), ■, ... Specified voltage.

Claims (2)

[Claims] (1) A level detector that detects whether the positive and negative voltages of the input pulse exceed specified values, a differentiator that differentiates the input pulse, and a zero point that detects the zero crossing point of the output pulse of this differentiator. In a peak detection circuit comprising a crossing detector and means for generating a peak pulse from the detection pulse of the zero crossing detector and the level detector, the means for generating the peak pulse is configured to generate a detection output of the level detector. A peak detection circuit characterized in that it includes a logic circuit that sends out an output pulse at the timing of the detection output of the zero crossing detector that is sent out immediately after. (2) The logic circuit includes an RS type flip-flop in which one of the positive and negative detection pulses of the level detector is used as a set input and the other is used as a reset input, and the output pulse of this RS type flip-flop is used as a data input, and the above-mentioned zero A peak detection circuit according to claim 1, which includes a D-type flip-flop that receives the output pulse of the crossover detector as a clock input, and a pulser that generates a peak pulse using the output pulse of the D-type flip-flop. .