JPS6282773A - Synchronizing signal correction circuit - Google Patents

Abstract

PURPOSE:To prevent the disturbance of a picture by changing the timing of the synchronizing signal of an internal video signal in response to the synchronization deviation between the synchronizing signal of the internal video signal and an external video signal. CONSTITUTION:A synchronizing correction control circuit 16 applies a control that the reproducing mode is changed over from the internal video signal into the external video signal and that the internal vertical synchronization signal generated in an internal vertical synchronizing clock generating circuit 20 and the internal horizontal synchronizing signal generated by an internal horizontal synchronizing clock generating circuit 18 are corrected in superimposing the internal video signal onto the external video signal and the result is approached gradually. A synthesis circuit 24 outputs the internal video signal when the reproduction mode of the internal video signal is instructed by the instruction of a synchronizing correction control circuit 16 and changes over the mode into the reproducing mode of the external video signal after the correction end of the internal synchronizing signal is awaited when the reproduction mode is switched from the internal video signal into the external video signal. Thus, picture disturbance is prevented.

Description

Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a synchronization signal for synchronizing an internal video signal contained in a video disc playback device with synchronization of an external video signal played from a video disc. Round to the correction circuit.

(Prior Art) As a function of a video disc playback device, there is a superimpose function that displays characters such as a screen number on a playback screen. In addition, although conventional video disc playback devices do not have this feature, it would be great if it were possible to display functions such as explanations of the device's functions and how to use them, or displays for demonstration purposes at stores, etc., when discs are not being played. It's convenient.

These functions are performed by the disc reproducing apparatus itself having an internal video generator 1 noter and reproducing signals from the video generator (hereinafter referred to as internal video signals). In this case, the internal video signal is used as the disc playback video signal.
This is called an external video signal. ), or when switching the playback from the internal video signal to the external playback signal or vice versa, synchronization of the internal video signal and the external video signal becomes a problem. In other words, the synchronization of the internal video signal is based on the crystal oscillation clock generated inside the device (it can be displayed even if the disc is stopped), whereas the synchronization of the external video signal played from the disc is included in itself. taken by the synchronization signal. Therefore, the internal video signal and the external video signal are synchronized independently of each other, and if the horizontal and vertical synchronization signals of both are not aligned in phase, the internal video signal will not be correctly positioned at the predetermined position on the screen when performing superimposition. The signal image is no longer displayed. Furthermore, when switching the playback mode from an internal video signal to an external video signal or vice versa, the image may flicker temporarily.

(Problems Solved by the Invention) The present invention solves the problems in the prior art, and makes it possible to smoothly synchronize the internal video signal with the synchronization of the external video signal. The present invention aims to provide a synchronization signal correction circuit that prevents image disturbances when switching playback modes or superimposing.

[Means for solving problems]

This invention detects the synchronization difference between the synchronization signal of the internal video signal and the external video signal, and according to the difference,
The timing of the synchronization signal of the internal video signal is changed little by little to gradually bring it closer to the synchronization signal of the external video signal, so that they match or almost match.

(Function) According to the solution of the present invention, the synchronization of the inner N5N image signal (hereinafter referred to as internal synchronization, in particular vertical synchronization is referred to as internal vertical synchronization, and horizontal synchronization is referred to as internal horizontal synchronization) is performed using an external video signal. synchronization (hereinafter referred to as external synchronization; in particular, vertical synchronization is referred to as external vertical synchronization, and horizontal synchronization is referred to as external horizontal synchronization), so the image when switching playback modes or superimposing can prevent disturbances. Furthermore, since the internal synchronization does not approach the external synchronization all at once, but gradually approaches it, image disturbances caused by changing the internal synchronization itself can be prevented by the synchronization change absorption and correction effect on the television.

〔Example〕

An embodiment of this invention is shown in FIG. In this example,
Vertical synchronization is corrected in units of one field of the internal video signal by reducing the number of scanning lines in each field. In addition, horizontal synchronization correction is performed using internal synchronization 18().
This is done by shortening each horizontal scanning period in units of (1) (between horizontal scanning WJ). And the order of correction is
The vertical synchronization is first corrected, and after that is completed, the horizontal synchronization is corrected.

In FIG. 1, the disc reproduction composite video signal is a signal obtained by FM demodulating the disc reproduction signal.

A synchronization signal separation/detection circuit 10 extracts a vertical synchronization signal EXVSYNC and a horizontal synchronization signal EXH8YN from an external video signal.
This is a circuit that extracts C.

The control circuit 12 receives a command CRCT for instructing synchronization correction;
This is a circuit that outputs a command VIDEO that instructs the reproduction mode of an external video signal. If a disc playback operation is performed while an internal video signal is being output, a synchronization correction command CR is issued.
CT is issued and synchronous correction operation is started. When the synchronization correction operation is completed, the disc reproduction command VIDEO and other signals to be described later switch to the external video signal reproduction mode.

internal! 1! The direct synchronization clock generation circuit 2o is a circuit for vertically synchronizing the internal video signal, and outputs a signal indicating the scanning line number of the internal video signal.

The internal horizontal synchronization clock generation circuit 18 is a circuit for horizontally synchronizing the internal video signal, and outputs a signal indicating the position of the internal video signal within one horizontal scanning period H.

The synchronization correction control circuit 16 uses internal vertical synchronization generated by the internal vertical synchronization clock generation circuit 20 when switching the playback mode from an internal video signal to an external video signal or superimposing an internal video signal on an external video signal. This control corrects the internal horizontal synchronization generated by the internal horizontal synchronization clock generation circuit 18 to gradually bring it closer to external synchronization.

The internal video signal generation circuit 22 is a circuit that generates an internal video signal for displaying explanations of the player's functions and how to use them, or for displaying demonstrations at stores.
An internal video signal is generated based on a scanning line number command from the internal vertical synchronization clock generation circuit 20 and a position command within one horizontal scanning period H from the internal horizontal synchronization clock generation circuit 18.

According to instructions from the synchronization correction control circuit 16, the synthesis circuit 24
The playback mode can be switched between an internal video signal and an external video signal for output, or both video signals can be superimposed and output. When the playback mode of the internal video signal is instructed, the internal video signal is output, and when the playback mode is switched from the internal video signal to the external video signal, the correction completion of the internal frequency 1j signal is indicated. Hold it to play the external video signal and switch to one mode. In this case, the signal selected by the combining circuit 24 is displayed on the television as a video output.

Further, when a playback mode in which an internal video signal and an external video signal are superimposed is instructed, a signal obtained by adding both video signals is displayed on the television after waiting for synchronization of the internal video signal to be completed.

Next, the internal configuration of each of the circuits 16, 18, and 20 will be explained.

(1) Synchronization correction control circuit 16 The AND circuit 24 in the synchronization correction control circuit 16 receives the time base collector ON signal TBCON from the synchronization signal separation detection circuit 10 and outputs the synchronization correction command CRCT from the control circuit 12. The correction permission command CREN is output only when the correction permission command CREN is specified. The time base collector is a control that removes jitter (fluctuation in the time axis direction) in the disc playback signal using a continuously variable evaluation circuit, etc. After the disc motor has started up and the disc rotation has stabilized, the control is performed. is started, and the time base collector signal TBCON is output at that time. Therefore, the correction permission command CREN is output from the AND circuit 24 after the disk rotation becomes stable.

The AND circuit 26 receives the correction permission command CREN from the AND circuit 24 and the disc reproduction command VI from the control circuit 12.
A signal obtained by inverting DEO with an inverter 28 is input. The disc playback command VIDEO is originally a command that can forcefully switch the playback mode to the external video signal side, but normally it is not issued until the synchronization correction is completed, so the output of the inverter 28 is it 1 u, and the correction permission command CREN is applied to the set input of the correction standby register 30 via the AND circuit 26 to set it.

The AND circuit 46 is turned on when the correction standby register 30 is set, the vertical synchronization standby register 36 is in a reset state (vertical synchronization mismatch), and the output of the inverter 718 is "1", and the vertical synchronization correction request signal VCOR is turned on.
Output. By outputting this signal VCOR, internal vertical synchronization clock generation circuit 20 starts an internal vertical synchronization correction operation.

The AND circuit 32 operates when the correction permission command CREN is output and the correction standby register 30 is set.
It is turned on at the timing when the external vertical synchronization signal EXVSYNC is output, and outputs the vertical synchronization determination signal VJDG.

This signal VJDG is the internal vertical synchronization clock generation circuit 2.
0 and used to detect the deviation between internal vertical synchronization and external vertical direction II.

The AND circuit 34 is connected to the internal vertical synchronization clock generation circuit 20
, a synchronization judgment signal ΔV is output when internal vertical synchronization and external vertical synchronization match.

It becomes operational, turns on at the timing of the vertical synchronization determination signal VJDG, and sets the vertical synchronization standby register 36. By setting the vertical synchronization standby register 36, it is confirmed that the vertical synchronization matches.

The AND circuit 40 outputs the output of the inverter 44 when the correction standby register 30 is set and the horizontal synchronization standby register 42 is in a reset state (horizontal synchronization mismatch).
°1", the vertical synchronization standby register 36 is set and turned on, and the horizontal synchronization correction request signal HCOR
Output.

By outputting this signal 1-(COR, the internal horizontal synchronization clock generation circuit 18 starts an internal horizontal synchronization correction operation.

The AND circuit 38 is turned on at the timing when the external horizontal synchronization signal EXH8YNC is outputted and outputs the horizontal synchronization determination signal HJDG in a state where the correction permission command CREN is output and the correction standby register 30 is set to 1-. This signal) IJDG is used to detect a deviation between internal horizontal synchronization and external horizontal synchronization.

The AND circuit 50 is an internal horizontal synchronization clock generation circuit 18
In this case, the horizontal synchronization coincidence detection signal Δ1''o outputted as soon as the internal horizontal synchronization and external horizontal synchronization match becomes operable, turns on at the timing of the horizontal synchronization determination signal HJDG, and sets the horizontal synchronization standby register 42. By setting the horizontal synchronization standby register 42,
It is confirmed that the horizontal synchronization is consistent.

The AND circuit 52 turns on when it is confirmed that the correction standby register 30, the vertical synchronization standby register 36, and the horizontal synchronization standby register 42 are all set, and that the internal and external vertical synchronization and horizontal synchronization all match.・Horizontal synchronization standby signal VH8TB
Output.

The AND circuit 54 outputs a vertical/horizontal synchronization standby signal VH.
When 8 TB is output and the disc reproduction command VIDEO is output from the control circuit 12, it is turned on at the timing when the field end timing signal TIM is output from the synchronization signal separation/detection circuit 10, and the external display register 56 is set.

When the external display register 56 is set, the external display signal EXDSP is output and the synthesis circuit 24
The output of is switched from internal video signal to external video signal,
Alternatively, these combined outputs are output as superimposed outputs. At the same time, the correction standby register 30, vertical synchronization standby register 36, and horizontal synchronization standby register 42 are reset. Further, when the external display register 56 is set and the external display signal EXDSP is output, the internal vertical synchronization clock generation circuit 20 and the internal horizontal synchronization clock generation circuit 1
8, which had been independently running independently up until now, now has their internal counters cleared at their respective timings by the external vertical synchronizing signal EXVSYNC and external horizontal synchronizing signal EXHS YNC. Therefore, after switching to the external video signal synchronization state, the internal video signal and the external video signal are always in synchronization, and the synthesis of mountain canyon image signals, that is, the superimpose function, can be stably realized. Also, when the disc playback is finished and the disc playback command VIDEO falls, the external display register 56 is reset via the inverter 58, and when the playback mode is switched from the external video signal to the internal video signal or the superimposition is canceled. Even when switching, the switching can be done smoothly without any synchronization correction.

Note that the field end timing signal TIM that sets the external display register 56 is output at the timing after 262 or 263 scanning for each field. Disturbances in vertical synchronization and unnatural screen switching caused by switching the playback mode to pause can be prevented.

(2) Internal vertical synchronization clock generation circuit 20 In the internal vertical synchronization clock generation circuit 20, the VGN counter 6
0 is an IC that performs internal vertical synchronization, and is counted up by the horizontal synchronization clock H8YNC, which is output at regular 1-to-1 cycles based on the crystal oscillation clock, and outputs a count value corresponding to the scanning line number. . That is, in the internal video signal reproduction mode, 0 to 262 (corresponding to the first field, that is, the first to 263rd scanning lines), 0 to 262
261 (corresponding to the second field, that is, the 264th to 525th scanning lines) are alternately self-traveled. To perform synchronization correction when superimposing or switching from an internal video signal to an external video signal, the clearing timing of the VGN counter 60 is advanced little by little (in other words, the period of one field of the cut is gradually advanced by gradually advancing the scanning line). This is done using internal synchronization. The number of scanning lines to be cut is determined within the followable range of the TV (cutting a large number within one field will cause the screen to be distorted), and if the difference between internal vertical synchronization and external vertical synchronization is large within that range, the number of cuts should be Increase the number of cuts, and reduce the number of cuts as the deviation becomes smaller. When the deviation reaches the minimum width (tolerable width that does not cause screen disturbance when switching from the internal video signal to the external video signal), the number of cuts becomes O. become. in this way,
By changing the number of cuts, vertical synchronization can be corrected quickly and reliably.

The VCR counter 62 determines the number of cuts of the scanning line; the larger the count value, the greater the number of cuts; the smaller the count value, the smaller the number of cuts. When the count value is 0, the number of cuts is 0.

The up/down control circuit 63 controls the VCR counter 62 up/down. The amount of deviation between internal vertical synchronization and external vertical synchronization is detected by checking the count value of the VGN counter 60, which is the internal vertical synchronization timing, at the output timing of the vertical synchronization judgment signal VJDG, which is the external vertical synchronization timing. can. and,
If the count value of the VCR counter 62 is small even though the amount of deviation is large, the AND circuit 64 is turned on at the timing of the vertical synchronization determination signal VJDG, and the VCR counter 62 is counted up. In addition, if the value of run 1 of the VCR counter 62 is large even though the deviation is small, the AND circuit 66 is turned on at the timing of the vertical synchronization determination signal VJDG, and the VCR counter 62 is run down. In this way, the VCR counter 62 is counted up or down depending on the deviation between the internal vertical synchronization and the external vertical synchronization, and an appropriate number of scanning lines to be cut is determined according to the amount of deviation.

The synchronous timing generation circuit 68 outputs a clear signal INVSY at the timing of the VGN counter 60 corresponding to the number of cuts specified by the VCR counter 62, and outputs a clear signal INVSY to the OR circuit 7.
Clear the VGN counter 60 via 0. That is, the VGN counter 60 counts 262 (first field) and 1! 261 counts (2nd field)
Since it is cleared before reaching O, the timing of returning to O is advanced, and the scanning line is cut by that amount.

Note that when the vertical synchronization correction command VCOR is not output, the switch 71 is turned off and the clear signal INVS
Since Y is no longer output, the VGN counter 60 has a normal count value (0 to 262 in the case of the first field,
In the case of a field, it cycles from O to 261).

The synchronization judgment circuit 74 outputs a synchronization judgment signal Δvo when the count value of the VCR counter 62 is O (that is, no cut) and the deviation between the external vertical synchronization and the internal vertical synchronization becomes the minimum (a range that can be absorbed by the television). do.

The AND circuit 72 becomes operational when the internal vertical synchronization and internal horizontal synchronization corrections are completed, the external display register 56 is set, and the external display signal EXDSP is output, and the external vertical synchronization signal EXVSYNC is output.
is added to the VGN counter 60 via the OR circuit 70 and reset. In other words, after synchronization correction is completed and superimposition is started, or after the playback mode is switched to an external video signal, the internal vertical synchronization is changed to the external vertical synchronization field by field to match the external vertical synchronization. Can be synchronized.

The count value of the VGN counter 60, which operates as described above, is input to the internal video signal generation circuit 22 as an indication of the scanning line number of the internal video signal, and is used to generate the video signal of the corresponding scanning line. be done.

(3) Internal horizontal synchronous clock regeneration circuit 18 In the internal horizontal synchronous clock regeneration circuit 18, the HGN counter 7
4 is for internal horizontal synchronization, and is counted up by 455 in one regular horizontal scanning period H based on the crystal oscillation clock, and outputs a count value corresponding to the horizontal position in one scanning line. When in the internal video signal reproduction mode, it automatically runs from 0 to 454. To perform synchronization correction when switching the playback mode from an internal dinner party signal to an external video signal when performing superimposition, the clearing timing of the HGN counter 74 is advanced little by little within the followable range of the television, and one horizontal scanning period H is applied. This is done by shortening the length little by little.

When correcting vertical synchronization, as mentioned above, the shortening of the period of one field was varied depending on the size of the deviation between internal synchronization and external synchronization, but when correcting horizontal synchronization,
The shortened version of 11H is used as one rate.

That is, switching between one horizontal scanning period is performed by the switch 76, and when synchronization correction is not performed, the switch 76 is connected to the a side and the OR switch is switched every 455 counts corresponding to one normal horizontal scanning period H. Cleared via circuit 78. Further, when performing synchronization correction, the switch 76 is connected to b* by the horizontal synchronization command HCOR,
Cleared every 450 counts. Therefore, the horizontal scanning period H of internal horizontal synchronization is shortened by 5 force counts for each scan, gradually approaching external horizontal synchronization. When the shift group between the internal horizontal synchronization and the external horizontal synchronization becomes small and enters the absorption range of the television, the synchronization determination signal ΔHo is output.

The reason why the internal horizontal synchronization correction amount in one scan is set to 5 counts is because horizontal synchronization is different from vertical synchronization in terms of television performance and can follow rougher signals.

The AND circuit 80 becomes operational when the internal vertical synchronization and internal horizontal synchronization corrections are completed, the external display register 56 is set, and the external display signal EXDSP is output, and the AND circuit 80 outputs the external horizontal synchronization signal EXH8YNC to an OR circuit. 78 to the HG N counter 74 and reset it. In other words, after synchronization correction is completed and superimposition is started, or after switching to external video signal playback mode, the internal horizontal synchronization is adjusted every scan to match the external horizontal synchronization. Can be synchronized.

Here, the operation of the circuit shown in FIG. 1 will be explained.

Before a disc playback operation is performed, the external display signal EXDSP is not output, so the internal vertical synchronization clock generation circuit 20 and the internal horizontal synchronization clock generation circuit 18 run freely, and the internal video signal generation circuit 22 outputs the internal video signal. The signal is read out and displayed on the television via the combining circuit 24.

When a disc reproduction command or a superimpose command is issued, a synchronization correction command CRCT is output from the control circuit 12. When the disk rotation becomes stable and the time base collector on signal TBCON is output, the AND circuit 24 is turned on and the correction standby register 30 is set via the AND circuit 26. This turns on the AND circuit 46, outputs the vertical synchronization correction request signal VCOR, turns on the switch 71 of the internal vertical synchronization clock generation circuit 20, and starts the internal vertical synchronization correction operation.

In the vertical synchronization correction operation, VJDG, which indicates internal vertical synchronization, is set to
Look at the count Iff of the GN counter 60, and if the difference is large, count up the VCR counter 62,
When the difference is small, the VCR counter 62 is counted down. Then, the count value of the VCR counter 62 determines the number of cuts of scanning lines in one field (the larger the count value, the larger the number of cuts), and the synchronization timing generation circuit 68 determines the period of one field by cutting the scanning lines. The VGN counter 60 is reset at the shortened interval, and the internal vertical synchronization is gradually brought closer to the external vertical synchronization. When the deviation between internal vertical synchronization and external vertical synchronization is large, increase the number of scan line cuts, and as the deviation h) decreases, reduce the number of cuts. Let the number of cuts be O.

When the count value O of the VCR counter 62 indicates that the deviation becomes almost O, the synchronization judgment signal Δvo is output, and the AND circuit 3
4, the vertical synchronization standby register 36 is set at the timing of the vertical synchronization determination signal VJDG. Now, the vertical synchronization correction request signal VCOR falls, the switch 71 is turned off, and the vertical synchronization correction operation is completed.

When the vertical synchronization standby register 36 is set, the AND circuit 40 is turned on and the horizontal synchronization correction request signal HCOR is output.
is output, and the horizontal synchronization correction operation is executed. That is, in the internal horizontal synchronization clock generation circuit 18, the switch 76 is connected to the b side, and the HGN counter 74 is set to the normal 1
450 from 455 counts corresponding to horizontal scanning period T1
The count will now be reset from 1.

With this, the internal horizontal synchronization is shortened by one horizontal scanning period H,
Gradually approaches external horizontal synchronization. Since this shortening period is slight, the Uma<FigJ period is locked on general television. When the internal horizontal synchronization approaches the external horizontal synchronization, a synchronization determination signal ΔHo is output.

When the synchronization determination signal ΔHo is output, the AND circuit 50 turns on at the timing of the horizontal synchronization determination signal HJDG corresponding to external horizontal synchronization, and sets the horizontal synchronization standby register 42. As a result, the horizontal synchronization correction request signal HCO
R falls, the switch 76 is returned to the normal a side, and the horizontal synchronization correction operation is completed.

When the correction of vertical synchronization and horizontal synchronization is completed as described above, the AND circuit 52 is turned on and the control circuit 12 outputs the disc playback command VIDEO. is turned on, external display register 56 is set, and external display signal EXDSP is output.

As a result, the combining circuit 24 switches and outputs the external video signal from the internal video signal, or combines and superimposes and outputs the signals, so that the video from the disc is displayed on the television. Also, at this time, registers 30, 36.
42 is reset.

Furthermore, when the external display signal EXDSP is output, the AND circuits 72 and 80 become operational, and the external vertical synchronizing signal EXVSYNC and external horizontal synchronizing signal EXH3YN
Timing of internal vertical synchronization and internal horizontal synchronization is determined by C. Therefore, even during disk playback, internal synchronization almost matches external synchronization, and stable superimposition is achieved. Further, when the playback mode of the external video signal is switched to the internal video signal after the disc playback is finished, the IJJ can be switched smoothly without correction.

FIG. 2 is a time chart showing the above correction operation.

When the synchronization correction command CRCT is output, a vertical synchronization correction operation is started, and the interval of the internal vertical synchronization signal INVSY is shortened so that it gradually approaches the external vertical synchronization signal FXVSY.

When they almost match, the vertical synchronization standby signal VSTB is raised, the vertical synchronization correction operation is completed, and then the horizontal synchronization correction operation is started. In the horizontal synchronization correction operation, the interval of the internal horizontal synchronization signal INH8Y is shortened and gradually approaches the external vertical synchronization signal EXH3Y, and when they almost match, the horizontal synchronization standby signal H8TB is set and the horizontal synchronization correction operation is started. finish.

All synchronization correction operations are now complete, the external display signal EXDSP is turned on, the internal video signal is switched to the external video signal playback mode, or superimposition is started, and the video from the disc or A composite image with the internal video signal is displayed.

A specific example of the internal vertical synchronization clock generation circuit 2o is shown in FIG.

The VGN counter 60 is counted up by the clock H8YNC corresponding to the horizontal synchronization signal based on the crystal oscillation output, and alternately counts 0 to 262 (first field) and o to 261 (second field) when reproducing the internal video signal. Here, in order to match the timing with other circuits, the count value 5 is used as the signal indicating the scanning line number.
It is assumed that it corresponds to the scanning line. ), and is sent to the internal video signal generation circuit 22.

Decoder 90 decodes the count value of VGN counter 60. Of the outputs of the decoder 90, ■ to ■ are for detecting the deviation between the external vertical direction 11 and the internal vertical synchronization, and ■ to ■ are for detecting the deviation between the external vertical direction 11 and the internal vertical synchronization, and the signals It is for clearing with.

In other words, the output ■ indicates count values 2 to 8, and is the interval closest to the count value 5, which is the reference timing of external vertical synchronization (deviation amount Δ■ 1), and the vertical synchronization determination signal VJDG is obtained within this interval. For example, it is determined that the internal vertical synchronization almost matches the external vertical synchronization.

Output ■ is count value 252 to 261 (or 262)
, 0.1, and in this section the vertical synchronization determination signal VJDG
If this is obtained, it is determined that the internal vertical synchronization and the external vertical synchronization are farther apart (deviation amount ΔV2) than in the case of output (2).

The output ■ indicates a count value of 234 to 251, and if the vertical synchronization judgment signal VJDG is obtained in this interval, it is determined that the internal vertical synchronization and the external vertical synchronization are farther apart than in the case of the output ■ (misalignment Δv3). Ru.

The output ■ indicates a count value of 9 to 233, and if the vertical synchronization determination signal VJDG is obtained in this interval, it is determined that the internal vertical synchronization and the external vertical synchronization are the most distant (difference Δ■4).

It should be noted that the expressions of the magnitudes of the deviation amounts Δ■ to Δ■4 described above are expressions taking into consideration the unidirectional correction operation as described below, and do not necessarily correspond to the magnitudes of the numerical values.

On the other hand, the output ■ shows a count value of 260, which means that VG
If the counter 60 is reset from N, one field ends one or two counts earlier than the normal interval of 261 or 262. This is used when the VCR counter 62 is 1, that is, when the internal vertical synchronization and external vertical synchronization are close.

The output ■ shows a count value of 257, and if the VGN counter 60 is reset with this, it will be 4 or 5 counts earlier than the normal interval of 261 or 262.
Field ends.

This is used when the VCR counter 62 is 2, that is, when the internal vertical direction II and external vertical synchronization are slightly apart, or when there is a transient state.

The output ■ shows a count value of 254, and if the VGN counter 60 is reset with this, it will be 7 or 8 counts earlier than the normal interval of 261 or 262.
Field ends.

This is used when the VCR counter 62 is 3, that is, when the internal vertical synchronization and external vertical synchronization are far apart.

The VCR counter 62 counts up/down from 0 to 3, and the count value corresponds to the amount of shortening of the interval of one field of internal vertical synchronization. In other words, the count value O has a reduction amount of 0 (the VGN counter 60 is reset at the normal count value of 261 or 262),
Count value 1 means the reduction amount is 1 or 2 (VGN counter 60 is reset at 260), count value 2 means the reduction amount M is 4.
or 5 (VGN counter 60 is reset at 257)
, a count value of 3 corresponds to a reduction amount of 7 or 8 (the VGN counter 60 is reset at 254), respectively.

The up/down control circuit 63 increases/decreases the VCR counter 62 according to the amount of deviation between the external vertical synchronization and the internal vertical synchronization so that the amount of shortening of one field has the above-mentioned relationship.
It counts down. The up/down conditions by the up/down control circuit 63 are shown in the table below.

↑: 1 count down ↓: 1 count up In the up/down control circuit 63, the AND circuit 92
When the VOR counter 62 is O, the VGN counter 60
The logic circuit in FIG. 3 is turned on at the timing of the output (■).The notation of the logic circuit in FIG. ), is output via the OR circuit 94, and at this time, the vertical synchronization determination signal V
When JDG is being output, the VCR counter 62 is incremented by one. Similarly, the AND circuit, 96.98,
100 also increases by one count under the conditions shown in the table above.

When the VCR counter 62 is 3, the AND circuit 102 outputs V
It turns on at the timing of the output (■) of the GN counter 60 and is output via the OR circuit 104. At this time, if the vertical synchronization determination signal VJDG is output, the VCR counter 62
count down by 1. Similarly, AND circuit, 106
, 108, and 110 also count down by 1 under the conditions shown in the table above.

In this way, the relationship of deviation ffi:VCR counter 62 becomes Δv:0 ΔV:1 Δv:2 ΔV ``3 4'', and the VCR counter 62 becomes stable.

Note that the inverter 12 prohibits the VCR counter 62 from going down when it is O, and the inverter 13 prevents the VCR counter 62 from going down.
When the counter 62 reaches 3, up-setting is prohibited.

In the synchronization timing generation circuit 68, the AND circuit 11
3 turns on at timing 260 of the VGN counter 60 when the VCR counter 62 is 1, outputs the internal vertical synchronization signal INVSY via the OR circuit 116, and resets the VGN counter 60. Similarly, AND circuit 118
When the VCR counter 62 is 2, the VGN counter 6
The AND circuit 120 turns on at timing 257 of 0, and when the VCR counter 62 is 3, the VGN counter 60
254, outputs the internal vertical synchronizing signal rNVsY via the OR circuit 116, and resets the VGN counters 60, respectively.

In the synchronization determination circuit 74, the AND circuit 122
When the R counter 62 is O, the VGN counter 60 2 to 8
It turns on at the timing of , and outputs the synchronization judgment signal ΔVo. By outputting this signal ΔVo, it is determined that the internal vertical synchronization almost matches the external vertical synchronization.

〔Effect of the invention〕

As explained above, according to the present invention, the internal synchronization is brought closer to the external synchronization, and these synchronizations match or almost match, thereby preventing image disturbances when superimposing or switching playback modes. It can be prevented. In addition, since the internal synchronization does not approach the external synchronization all at once, but gradually approaches it, these changes are within the range that can be tracked by the TV and J:kV)' This prevents image disturbances caused by shifting the internal synchronization itself. be able to.

[Brief explanation of drawings]

The first is a block diagram showing an embodiment of the present invention. FIG. 2 is a time chart showing the correction operation of the internal synchronization signal by the circuit of FIG. 1. FIG. 3 is a circuit diagram showing a specific example of the internal vertical interval 1g clock generation circuit 20 of FIG. 16...Synchronization correction control circuit. 18... Internal horizontal synchronization clock generation circuit, 20... Internal vertical synchronization clock generation circuit.

Claims (1)

[Scope of Claims] 1. An internal video signal generation circuit for outputting an internal video signal included in the video disc playback device, and a synchronization signal for detecting a synchronization signal in an external video signal played from the video disc. a detection circuit, a synchronization signal for the internal video signal, a synchronization shift detection circuit for detecting a synchronization shift between the external video signal, and a synchronization shift detection circuit for detecting a synchronization shift between the internal video signal and the external video signal; hand,
A synchronization signal correction circuit comprising: a control circuit that gradually brings the synchronization signal of the external video signal closer to the synchronization signal to match or substantially match the synchronization signal. 2. When the synchronization difference is large, the amount of change in the timing of the synchronization signal of the internal video signal is increased, and when the difference is small, the amount of change in the timing is decreased. The synchronization signal correction circuit according to item 1.