JPS622292A - Image display unit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image display device that displays an image generated by an external video signal superimposed on, for example, an image created by a computer (so-called superimposition).

In this case, superimposing is not only a case of completely switching and replacing two images, but also a case where one image is displayed superimposed on the other image, and the two images overlap. It shall also include a visible aspect.

[Summary of the invention]

In the present invention, when superimposing a first video signal and a second video signal in synchronization,
The phase of the synchronization signal of the second video signal is shifted from the first video signal by a set value, and by changing this set value, a display screen based on the second video signal can be created in any area of the display screen. It is possible to display any part of the area.

[Conventional technology]

BACKGROUND OF THE INVENTION It is often used in the fields of information services and computer games to superimpose a computer graphics screen and a reproduced image from a VTR or video disc and display the superimposed image on a monitor screen. For this reason, even in image display control LSIs (called CRT controllers or video display processors), computer graphics images and V
Some have a superimposition function with an external video signal from a TR or the like.

Figure 5 shows an example of this type of image display device, and Tl) is a so-called video RAM in which image data for one screen is stored.
and CPU (any character by 21).

Image data such as figures is written. In this case, the image data is data of one dot each obtained by dividing the screen of the monitor receiver (6) into n dots horizontally and m dots vertically.

(3) is an image display control unit having, for example, an LSI configuration, which generates read addresses, memory control signals, and internal horizontal and vertical synchronization signals for the video RAM (1), and displays data in dot units from the video RAM (1). The bit information of is read out as video data.

Furthermore, in this case, this image display control section (3) has a function of superimposing the external video signal, and therefore the CP
Image display control unit (3) according to instructions from U (2)
A switch circuit (3S) is provided which is switched by a switching signal obtained from the switch.

Then, a synchronizing signal 5YNC1 (FIG. 6A) of the external video signal EXV as described later from the input terminal (7) is supplied to the image display control section (3).
) The internal synchronization signal 5YNC2 (FIG. 2B) obtained in the above-mentioned signal is set to have a phase that matches that of the synchronization signal 5YNCI, and the two are synchronized.

The data read out from the video RAM (11) is converted into an analog video signal by the D/A converter (4), and the analog video signal INV is supplied to one input end of this switch circuit (3S). .Also, an external video signal EXV such as a playback signal from a VTR or video disc is input from the terminal (7) to this switch circuit (3S
) is supplied to the other input end of the Then, this switch circuit (3s) is switched from one input terminal to the other input terminal in a designated area portion of the screen, and an image generated by the external video signal EXV is displayed on a part of the screen by the signal INV generated by the computer. A corresponding part of the image is obtained by superimposing the image, and this is supplied to the monitor receiver (6) via the amplifier (5) to obtain a composite screen as shown in FIG. 7A.

In the case of this conventional device, as mentioned above, the external video signal E
It is used in conjunction with the synchronization of the image display control unit (3) with respect to
Cz (Fig. 6A) is supplied to the image display control section (3), and the synchronization signal 5YNC2 of the video signal from the D/A converter (4) is supplied to the synchronization signal 5YNC as shown in Fig. 6B.
It is assumed that the phase coincides with z.

Note that in the above example, the switch (3s) was changed to completely replace and superimpose the image from the video RAM ill and the image from the external video signal, but by adding the two, It is also possible to display an image from an external video signal superimposed on top of the tingling image.
0-56324).

[Problem that the invention seeks to solve]

As mentioned above, in superimposing an external video signal using a conventional image display control LSI, the image display control LSI is synchronized with the external video signal. The positional relationship between the video signal and the external video signal was determined. In other words, when the partial image shown by area + a) in Figure 7B is superimposed on a computer image, it will only be superimposed on areas with exactly the same positional relationship on the screen, as shown in area (b) in Figure 7A. It is not possible to pose, and it is not possible to insert a partial image of area (al) into an arbitrary area, such as the area (C) indicated by a dotted line in A of the same figure.

[Means for solving problems]

In this invention, the synchronization signal of the first video signal, for example, a video signal created by computer graphics, is shifted in phase with respect to that of the second video signal, for example, an external video signal, and the amount of the phase shift is shifted. Make it possible to set. Then, in an arbitrary area specified on one screen of the first video signal, the image of the period of this area of the second video signal is displayed superimposed on the first video signal.

[Effect]

The image area of the second video signal corresponding to the period of the area specified on the screen of the first video signal changes depending on the phase shift of the synchronization signal between the first video signal and the second video signal. Therefore, by selecting the amount of phase shift, a portion of an arbitrary image area of the second video signal can be superimposed on a designated area on the screen of the first video signal.

In other words, any desired partial image of the screen of the second video signal can be superimposed on any desired position of the screen of the first video signal.

〔Example〕

FIG. 1 shows an embodiment of the device of the present invention, and parts corresponding to those in the example in FIG. 5 are given the same reference numerals.

First, the CPU (2) switches the switches 81 to S3 to the B side and transfers the data and addresses of the video RAM (11) and the mask pattern RAM (11) to the CPU (2).
21, write screen data to the video RAM (11) from the CPU T21, and specify the area where the external video signal will be superimposed on the screen of the video RAM (1) to the mask pattern RAM (11). For example, the mask pattern RAM (11) has the same address as the video RAM (11), and the same address as the address of the superimposed area of the video RAM (1) is written with "1".
", data "0" is written to the other addresses, and the area of data "1" becomes the superimposed area.

Next, in the screen display mode, the switches 81 to S3 are switched to the A side, and the addresses of the video RAM (1) and mask pattern RAM (11) are switched to the addresses from the display address generator (12). The display address generation section (12) receives an internal horizontal synchronization signal H and an internal vertical synchronization signal V from the horizontal and vertical synchronization signal generation section (20).
and (21), these synchronization signals H and V
Address data for reading out the dot-by-dot data of RAM (1) and (11) in the form of a video signal is obtained from this.

Then, according to this address data, screen data is read out from RAM (1) and area designation signal is read out from mask pattern RAM (11).

The screen data from the video RAM (1) is supplied to the D/A converter (4) via the switch S2, converted into an analog signal INV, and supplied to one input end of the switch circuit (3S). On the other hand, the external video signal EXV from the input terminal (7) has the synchronizing signal removed by the synchronizing signal removal circuit (13) and is supplied to the other input terminal of the switch circuit (3S). And mask pattern RAM
The area designation signal from (11) is supplied to the switch circuit (3S) as a switching control signal through switch S3,
When the area designation signal is "0", the state is switched to the state shown in the figure, and when it is "1", the state is switched to the state opposite to the state shown in the figure.

Therefore, from this switch circuit (3S), the analog signal INV of the screen data from the video RAM (1) is obtained in areas other than the designated area, and the external video signal EXV is obtained in the designated area, and is superimposed. Become.

In this case, the external video signal and video RAM
When synchronizing with the screen data from (1), the synchronization signal for the video signal INV and the synchronization signal for the external video signal EXV are synchronized with a phase shift of the setting value preset from the CPU (2). Take.

That is, the external video signal EXV from the input terminal (7)
is supplied to a sync separation circuit (14), from which horizontal sync signals HD and VD are obtained.

The separated horizontal synchronization signal 1 (D) is supplied to one input terminal of the phase comparison circuit (15). On the other hand, the horizontal synchronization signal H from the horizontal synchronization generation section (20) is supplied to the delay counter section (18). ) to the other input terminal of the phase comparison circuit (15).The delay counter section (1B) receives the signal from the horizontal synchronization generation section (20) according to the preset value from the horizontal delay preset register (19). H is delayed by ΔH, and the CPU (21
The preset value is set from . Therefore, this preset value can be changed arbitrarily.

Therefore, in the phase comparator circuit (15), the horizontal synchronizing signal H
D and signal H', which is a delayed internal horizontal synchronization signal H from the horizontal synchronization generator (20), are compared in phase, and the phase error output is sent to the variable frequency oscillator (17) via the low-pass filter (16). and its oscillation frequency is controlled. The oscillation output signal of this variable frequency oscillator (17) is supplied to a horizontal synchronization generator (20).

This horizontal synchronization generating section (20) divides the frequency of the oscillation output signal to form an internal horizontal synchronization signal H.

The above closed loop constitutes a PLL circuit, and as a result, the oscillation frequency of the variable frequency oscillator (17) is controlled, so that the horizontal synchronization signal HD and the internal horizontal synchronization signal H are set to ΔH as shown in FIG. Phase synchronization is applied with a phase difference.

Next, in the vertical synchronization generation section (21), an internal vertical synchronization signal (■) is generated from the internal horizontal synchronization signal H and the oscillation output signal of the variable frequency oscillator (17). The synchronization signal VD is sent to the delay counter section (
22) and is delayed by Δ■ through the vertical synchronization generator (22).
1) is supplied to the reset terminal of the internal vertical synchronization signal■
is delayed by Δ■ with respect to the vertical synchronizing signal VD, as shown in FIG. Delay amount Δ at delay counter section (22)
V is determined by the preset count value from the vertical delay preset register (23), and this recent count value is set by the CPU (2) and can be changed arbitrarily.

In this way, the horizontal and vertical synchronization generators (20) and (21
), internal horizontal and vertical synchronization signals H and V are obtained which are out of phase by ΔH and ΔV with respect to the horizontal and vertical synchronization signals HD and VD of the external video signal EXV, and based on these, the video RAM (1) and mask pattern RAM
(11) While the data is read out, these internal synchronization signals H and V are output as synchronization signals for the monitor receiver.

Therefore, if the display screen of the monitor receiver is shown with diagonal lines in Fig. 3, the synchronization signal HD of the external video signal
And the screen by VD has ΔH in the horizontal direction as shown in the same figure.
and is shifted by 67 minutes in the vertical direction.

Therefore, if the superimpose area specified by the mask pattern RAM (11) is area d shown with diagonal lines in the screen on the right side of FIG. The screen includes area e (Video R
An external video signal is obtained at A M (same as area d on 11). The external video signal superimposed at this time is the signal portion extracted in area e in the screen shifted by the external video signal, indicated by the dotted line in the left-hand diagram of FIG. Therefore, the deviation amounts ΔH and Δ
By changing V, that is, by changing the preset values of registers (19) and (23), any screen portion of the external video signal can be displayed in area e.

In addition, area e is C in the mask pattern RAM (11).
Since this can be changed by changing the area d specified from P U (2), any screen portion of the external video signal can be superimposed on any area.

Then, for example, the specified area of the mask pattern RAM (11) and the vertical deviation ΔV are fixed, and the horizontal deviation ΔH is set in the register (19) so as to increase sequentially.
As you change the preset values, the external video screen shown by the dotted line in the left side of Figure 4 will move sequentially from left to right on the diagram, and if area e is a window, for example,
The image from the external video signal is I! If it is a single landscape picture, the display screen will be such that the landscape seen through this window is scrolled in sequence in the horizontal direction.

Similarly, by fixing the horizontal shift ΔH and sequentially varying the vertical shift ΔV, a display screen will be created in which partial images based on the external video signal scroll in the vertical direction within the area e.

Note that the method of synchronizing the horizontal and vertical synchronizing signals HD and VD of the external video signal and the internal horizontal and vertical synchronizing signals H and ■ with phase shifts ΔH and ΔV is not limited to the example shown in the figure, but can be performed by, for example, horizontally.

A PLL circuit configuration may be used in both the vertical direction, or a configuration in which only delay counters are used in both the horizontal and vertical directions. Other synchronization methods may also be used.

〔Effect of the invention〕

As described above, according to the present invention, when two types of video signals are synchronized with each other and a partial screen of the screen according to the other video signal is superimposed on the screen according to one video signal, Any part of the image can be superimposed on any area.

It is also possible to scroll only the images within the superimposed area.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an example of the inventive device, FIGS. 2 to 4 are explanatory diagrams, FIG. 5 is a block diagram of an example of an image display device, and FIGS. 6 and 7 are conventional FIG. 3 is a diagram for explaining the device. (1) is the video RAM, (2) is the CPU, (3S) is the switch circuit, (11) is the mask pattern RAM, (14) is the
) is a synchronization separation circuit, (18) and (22) are delay counters, (19) and (23) are preset value registers that determine the amount of phase shift, (2o) and (21) are horizontal and vertical synchronization generation Department. p yumibu ii included tile ii tachisai gTbanomiya gLI! Month m Figure 2 Figure 4 Figure 5 Q Period A Nail Blind Love Sun Moon Figure 6 Composite screen Outer depression σrxeu surface display screen f
Its word clam B moon map figure 7

Claims (1)

[Claims] A second video signal is synchronized with the phase of the synchronization signal being shifted by a set value from the first video signal, and the image displayed on the monitor screen by the first video signal is An image display device in which an image of a period corresponding to the area of the second video signal is superimposed on an arbitrarily designated area on the image.