JPS6282439A - False trouble generating system - Google Patents

Abstract

PURPOSE:To generate a false trouble even when a coincidence signal occurs at the second and following times, by detecting the coincidence between the address of program for the occurrence of the false trouble and the address of the executing program. CONSTITUTION:The program address which is fetched from a main storage device 1 and where the false trouble should be generated is set to a false trouble address register 10, and the value which is fetched from the main storage device 1 and is obtained by subtracting one from the number of times of coincidence is set to a counter 12. If the coincident between the output of an instruction count register 9 and the output of the false trouble address register 10 is detected by a coincidence detecting circuit 11, a coincidence signal is outputted through a signal line 110 to count down the counter 12. If the coincidence signal is outputted once more after the value of the counter 12 becomes 0, a borrow signal is outputted from the counter 12 to indicate the occurrence of the false trouble to a false trouble generating circuit 13 through a signal line 111.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for generating a pseudo-disabled person in an information processing device, and particularly to a method for generating a pseudo-disabled person based on matching of program addresses.

[Conventional technology]

Conventionally, in this type of pseudo fault generation method, a pseudo fault is generated when the execution address of the program module matches a preset value.

[Problem that the invention seeks to solve]

In the conventional pseudo-disabled generation method described above, if the corresponding program is executed multiple times.

Since a pseudo failure can only occur in the first case,
In the second and subsequent cases, there was a drawback that a pseudo failure could not be generated.

SUMMARY OF THE INVENTION The object of the present invention is to eliminate the above-mentioned drawbacks and to generate a pseudo fault by using a matching circuit which outputs a matching signal when it detects a match between the address of a program and the address of an executing program.

Even if the coincidence signal occurs η times (71 is a positive integer),
The object of the present invention is to provide a pseudo-failure generating force formula that can generate a pseudo-fault.

[Means for solving the problem 1] The method for generating a pseudo-disabled person of the present invention includes, in an information processing device,
a pseudo-fault address register (10 in FIG. 1) that holds a block address for generating a pseudo-fault;
iii pseudo-fault address setting means (1 in Figure 1) for setting the address of the program in the pseudo-old fault address register, the address of the program held in the pseudo-fault address register, and the address of the program being executed; A matching circuit (
11) in FIG. 1, and a match number holding means (12 in FIG. 1) that holds the number of matches.

If the number of matches set by the matching number setting means (1 in FIG. 1) which sets the number of matches in the matching number holding means and the number of times the matching signal is output from the matching circuit match the number of matching held by the matching number holding means, a pseudo Means of causing failure (13 in Figure 1)
It is characterized by having the following.

〔Example〕

Next, one embodiment of the present invention will be explained with reference to the drawings.

FIG. 1 is a block circuit diagram of one embodiment of the present invention.

The execution of the program in Tsugu is from main memory 1 to the instruction count register? After fetching the instruction at the address indicated by and storing it in the instruction register 5, the control circuit 5 is activated to interpret the instruction and execute the instruction. Let's do i11. Address adder 6 for fetching operands or storing results
The result of the calculation is temporarily held in the all-address register 7, and a request is issued to the storage device 1 (21). Fetch data is transmitted through signal line 101'i.

Store data is sent to the main storage device 1 via the data register 8. The arithmetic circuit 2 is controlled by the control circuit 6 and performs arithmetic operations according to various instructions.

The pseudo fault address register 10 is set by a software instruction.
The program address fetched from the main memory 1 for generating a pseudo failure is set. The counter 12 is set with a value equal to the number of matches fetched from the main memory 1 minus 1 by a software instruction. The coincidence circuit 11 is.

When a match between the output of the instruction runt register 9 and the output of the pseudo fault address register 10 is detected, a match signal is outputted through the signal line 110.

Instructs the counter 12 to count down. After the counter value reaches O, when a match signal is output again, a borrow signal is output from the counter 12, and the signal line 114
The pseudo-fault generation circuit 13 is instructed to generate a pseudo-fault.

〔Effect of the invention〕

As described above, the present invention has the advantage that all pseudo faults can be caused to occur when a match signal is generated n times (n is a positive integer) from a matching circuit that outputs a pseudo fault signal. That is.

Increase the number of cases of false failures 3.

[Brief explanation of drawings]

FIG. 1 is a block circuit diagram of one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Main memory device, 2... Arithmetic circuit, 3... Control circuit, 4... Instruction data fetch/store circuit. 5...Instruction register, 6...Address adder, 7.
・Address register, 8 ・Data register, 9・
. . . Instruction count register, 10 . . . Pseudo failure address register, 11 . . . Match circuit, 12 . . . Counter. 16...Pseudo fault occurrence circuit.

Claims (1)

[Claims] 1. In an information processing device, a pseudo-fault address register that holds an address of a program for generating a pseudo-fault, a pseudo-fault address setting means for setting a program address in the pseudo-fault address register, and the pseudo-fault address register. a matching circuit that outputs a matching signal when it detects a match between the address of the program held in the program and the address of the program being executed; a matching number holding means for holding the number of matches; and a matching number set in the matching number holding means. and means for generating a pseudo failure when the number of times the matching circuit outputs a matching signal matches the number of matching held by the matching number holding means. How it occurs.