JPS6278616A - Stand-by control system in cut-off mode of power supply - Google Patents

Abstract

PURPOSE:To prevent the malfunction of each peripheral equipment by making use of a stand-by function to separate a CPU from each peripheral equipment when the level of the input voltage drops. CONSTITUTION:A voltage detecting circuit 12 detects the drop of the power supply voltage VCC given from a D/D converter 11 and delivers the detection signals to a resetting circuit 13 and a stand-by signal generating circuit 14 when the voltage VCC is lower than a prescribed threshold level. The circuit 14 latches the detection signal and sends a stand-by signal of an L level to a stand-by signal input terminal 17. While the circuit 13 sends a resetting signal of an L level to a resetting signal input terminal 16. A CPU 15 is set under a stand-by state before it is reset. While output ports 18A, 18B, etc. are set in the high impedance states. Thus the mistaken output of the control signals is prevented to the peripheral equipments 19A, 19B, etc.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a small-sized one-viewer system, such as a hand belt computer.

Especially when the power is turned on/off, the CPU goes out of control.

The present invention relates to a standby control system for preventing peripheral devices from malfunctioning and at the time of power-off.

[Prior Art] In a small computer computer system such as a hand belt computer, the power may be turned on and off frequently. Conventionally, when the power is turned off, When a drop in the input voltage is detected, a so-called non-maskable included (NMI) interrupt is raised to C1), and the NMI interrupt handler is activated for several milliseconds until the power supply is completely stopped.・In Chin et al., L was used to perform processing such as stopping @l+ operations of various peripheral devices.

[Problem that the invention seeks to solve]

However, the processing by the above NMI interrupt.

For example, if it takes several tens of milliseconds, or if the time from when the input voltage begins to drop until it is completely shut off is short, the processing by the NM+ interrupt will not be completed, and the CP
There has been a problem in that the operation of U becomes unstable due to insufficient voltage, resulting in runaway operation. For example, CPt,
The printer etc. connected to the output port of J operates when the output port becomes I'J- level, but the CPH
As a result of runaway, the output port may become undesirably low I/hell, resulting in malfunction.

[Means for solving problems]

In order to solve the above problems, the present invention focuses on using the standby function used in the low power consumption mode of CPtJ, and when a voltage drop is detected, the detection signal is latched and the CPU A standby signal is supplied, thereby placing each port of the CPU in a high impedance state and stopping the operation of each peripheral device.

〔Example〕

FIG. 1 shows the configuration of an embodiment of the present invention, FIG. 2 shows a time chart 1-1 of an embodiment of the invention, and FIG. 3 shows a circuit diagram of a main part of an embodiment of the invention.

In FIG. 1, numeral 11 is a D/Dl converter that outputs a power supply voltage Vcc of, for example, 5cm, and numeral 12 is a D/Dl converter that outputs a power supply voltage Vcc of, for example, 5cm.

a voltage detection circuit that detects a drop in voltage; 13 a reset circuit that outputs a reset signal when the power is off; 14;
1 is a standby signal generation circuit that latches the detection signal of the voltage detection circuit B12 and generates a standby signal; 15 is a CPU that processes data by executing a predetermined command; 16 is a reset signal input terminal; 17 is standby signal input terminal, 18A, 18B are output capo~)
, 19A.

19B represents various peripheral devices such as a printer.

The cpuis has a standby function used in a so-called low power consumption mode, and when the standby signal input terminal 17 becomes low level, the internal clock is fixed and the CPU enters a standby state. Automatically by the hardware inside the CPU 15 when in standby mode.

Various ports 8A, 1813, etc. are in a high impedance state, and CPtJ15 is essentially 3 types of peripheral devices 1.
It is designed to be separated from 9A, 19B, etc.

For example, like the time chart 1 shown in FIG.

When the power is turned on and Vcc reaches a predetermined dark value -H, the voltage detection circuit 12 detects the voltage and cancels standby, and after a predetermined time, the reset circuit 13 cancels the reset signal. is made, and Sisteno is activated.

When the power is turned off, Vcc, for example 5V, begins to drop, and when it falls below a predetermined dark value, the voltage detection circuit 12 outputs a detection signal to the reset circuit 13 and standby signal generation circuit 14. . The standby signal generation circuit 14 immediately latches the detection signal and sends a low level standby function 5TBY to the standby signal input terminal 17. In addition, the reset circuit 13+ also outputs a low level reset signal RES- to the reset signal input terminal 7-16.
Send out.

The CPU 15 is in standby state t before being reset.
Since the input and output capacitors 188, 18B, etc. are in an impedance state, the output of incorrect control signals to the two peripheral devices 19A, 198, etc. is prevented.

Note that 1.L standby signal 9, for example, LCD display L
・I1, CD (not shown) lycee node message-q-IT
By using it as a RES, it is also possible to turn off the liquid crystal display, etc.

FIG. 3 shows a fourth circuit example of a portion related to generation of a standby signal. In FIG. 3, code numbers 4 to 17
20 is a flip-flop 521, 22 is a data bus, and 23 is an NMI interrupt input terminal.

24 represents an output port. In the 4-circuit shown in FIG. 3, the voltage drop detection signal, which was conventionally used for NMI interrupt 1, is sent to the preset terminal f) R? of the Nori-knob flop 20. I'm leading this.

Note that in the present invention, this detection signal may be separated from the NM+interruption 7 input terminal 23 so that NM+interruption 7 does not occur.

The reset signal is supplied to the reset signal input terminal 16 and also to the clear terminal CLR of the flip-flop 20.
Clears the flip-flop 20 at the start of CI"[J]5.

The power drop detection signal is sent via the preset terminal PR.
The output page of the flip-flop 20 is supplied to the standby signal input terminal 17 as a standby signal τ〒T3■. This results in
Output port 24 immediately goes into a high impedance state.

〔Effect of the invention〕

As explained above, (1) according to the present invention, even when the NM1 interrupt processing (C) and (2) the necessary voltage cannot be maintained during power-off, the CPU is substantially disconnected from each board in advance. Therefore, malfunctions of various peripheral devices can be prevented.

[Brief explanation of drawings]

FIG. 1 shows a configuration of an embodiment of the present invention, FIG. 2 shows a time chart 1 of an embodiment of the invention, and FIG. 3 shows a circuit diagram of a main part of an embodiment of the invention. In the figure, 11 is a l)/D converter, 12 is a voltage detection circuit, 13 is a seven-node circuit, 14 is a standby signal generation circuit, 15 is a CPLJ, 16 is a recent signal input terminal,
Reference numeral 17 represents a standby signal input terminal, 18A and 18B represent output ports, and 19A and 19B represent peripheral devices.

Claims (1)

[Claims] A standby signal to the standby signal input terminal (17) causes output ports (19A, 19B) to be output to peripheral devices (19A, 19B).
18A, 18B) to high impedance (
15), a voltage detection circuit (12) that detects a drop in input voltage, latches the output of the voltage detection circuit (12), and supplies a standby signal to the standby signal input terminal (17). a standby signal generation circuit (14), and a standby control system during a power cut, characterized in that the CPU (15) is isolated from the peripheral devices (19A, 19B) by supplying a standby signal when the input voltage drops. .