JP2580673B2 - Power control device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply control device used for an information processing device or the like, and more particularly to a power supply control device having an improved processing method when a power supply abnormality occurs. .

[Conventional technology]

A stabilized power supply is indispensable even in a system using a microcomputer, various information processing devices, or ordinary electronic devices, and various types of devices have been devised and used. On the other hand, even with such a stabilized power supply,
If the power supply does not operate normally, expensive devices may be destroyed, and various measures have been taken. There is also known a method in which a power failure (hereinafter referred to as an alarm) signal is generated when a power failure occurs and the power is turned on again after the failure is eliminated.

FIG. 3 is a block diagram showing a power supply control device for controlling the turning on and off of the power supply by this kind of alarm signal, and FIG. 4 is a timing chart showing the operation of the power supply control device.

When an on / off signal 12 for the power supply 11 is received from a higher-level device (not shown), the on / off signal 12 is supplied to an AND circuit (hereinafter referred to as an AND circuit) 15 of the power supply control circuit 14 of the power supply control device 13.
Is input to The output of the AND circuit 15 becomes a turn-on / turn-off signal 16, and further becomes a turn-on / off signal 18 through an OR circuit (hereinafter referred to as an OR circuit) 17, and is sent to the power supply 11. Power supply 11
Is turned on and off by this. Here, if there is any abnormality in the power supply 11, an alarm signal 21 is generated, which is input to the negative input terminal of the AND circuit 15 of the power supply control circuit 14. Since the alarm signal 21 at this time is at logic level 1, a signal of level 0 is input to the negative input terminal of the AND circuit 15. Therefore, the input signal of the input / output signal 12 from a higher-level device (not shown) is inhibited, and the AND circuit 1
The ON / OFF signal 16 which is the output of 5 is at logic level 0, the ON / OFF signal 18 of the output of the OR circuit 17 is also at 0 level,
11 is cut. Thereafter, a power-on / off signal 12 is sent from a higher-level device (not shown) to the power control device 13, and when a power-on instruction is given (a in FIG. 4), the power control circuit 14 generates an alarm reset signal of the power control device 13. A reset signal generation instruction signal 21 is issued to the circuit 20. This reset signal generation circuit
20 sends a reset signal 22 to an alarm signal latch circuit (not shown) built in the power supply 11 through the OR circuit 17 (b in FIG. 4). Thus, the alarm signal latch circuit (not shown) is reset, and the alarm signal 21 is reset. By resetting the alarm signal 21 in this manner (c in FIG. 4), the on / off signal of the on / off signal 16 which has been inhibited together with the generation of the alarm signal 21 becomes valid again (d in FIG. 4). By the way, the reset signal 22 is pulsed on the power-on signal line, that is, the OR circuit.
Since the input / output signal 17 is supplied to the reset signal 22, the reset signal 22 is superimposed before the input / output signal 18 is supplied as shown in FIG. Therefore, the output of power supply 11
V _OUT is once turned on, then turned off, and turned on again, as shown in FIG. 4f, resulting in an unstable state. After this state, the output _VOUT becomes stable. At that time, a closing completion signal 25 (g in FIG. 4) is sent to the power supply control circuit 14, and the closing is completed.

[Problems to be solved by the invention]

As described above, in the conventional power supply control device, when the power supply is turned on again after the power supply abnormality processing, the reset signal for canceling the alarm signal is given in a pulse form on the power-on signal line. For this reason, there arises a problem that the output voltage of the power supply gives an undesired pulsed output before the output state becomes stable. This has the disadvantage of adversely affecting the logic device as a load.

Therefore, an object of the present invention is to provide a power supply control device capable of preventing unnecessary output from occurring before the power supply output becomes constant when the power supply is turned on again after an alarm is generated, and solving the conventional problems. is there.

[Means for solving the problem]

The power supply control device of the present invention includes a circuit for enabling a power supply abnormality signal while a power supply signal is given, and a power supply signal from a host device or the like when the power supply once cut off due to a power supply failure is restarted. A power supply abnormality signal reset signal generation circuit for receiving and outputting a reset signal; and a circuit for resetting the power supply abnormality signal by a reset signal from the power supply abnormality signal reset signal generation circuit.

Therefore, using the power supply control device according to the present invention,
If there is no power-on signal, disable the alarm signal and
In addition, by resetting the alarm signal regardless of the power-on signal line when the power is turned on again after the occurrence of the alarm, it is possible to prevent the pulse-like power output which conventionally occurs before the power output becomes constant.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to examples.

FIG. 1 is a block diagram showing a power supply control device of the present embodiment,
FIG. 2 is a diagram showing the operation timing chart. 3 and 4 are designated by the same reference numerals,
The description thereof will be omitted as appropriate.

In the figure, an on / off signal 12 for a power supply 11 from a higher-level device (not shown) is a power supply control circuit of the power supply control device 12.
The signal is supplied to one input terminal of an AND circuit 15 constituting 14. The on / off signal 16 output from the AND circuit 15 is sent to the power supply 11, which supplies the output voltage _VOUT . The other input terminal of the AND circuit 15 takes a negation. The alarm signal 17 from the power supply 11 is input to the negative input terminal through the AND circuit 18 which is a feature of the present invention, becomes the second alarm signal 19, and is input as the third alarm signal 21 through the latch circuit 20. .

The other input terminal of the AND circuit 18 is connected to the AND of the power control circuit 14.
An on / off signal 16 output from the circuit 15 is branched and input. When the ON / OFF signal 16 is not the ON signal, a logical 0 level is input to the AND circuit 18, so that even if the first alarm signal 17 is present, the second alarm signal 19 becomes 0, and the alarm is invalid, that is, the alarm is disabled. It is the same as there is no. This alarm is enabled only when the ON / OFF signal 16 is the ON signal. The latch circuit 20 is used when the power supply 11 once turned off due to a power supply failure is turned on again. That is, when the ON / OFF signal 12 is given to the alarm reset signal generation circuit 24 from a higher-level device (not shown), the alarm reset signal generation circuit 24 sends a reset signal 25 to the latch circuit 20. The latch circuit 20 receiving this resets the second alarm signal 19. That is, when the second alarm signal 19 is 1, the output of the third alarm signal 21 is 0. Further, when the power supply is completed, the power supply 11 sends a power-on completion signal 26 to the power control circuit.
14, whereby the power supply 11 provides a constant output _VOUT .

 Next, the operation of this apparatus will be described with reference to FIG.

When a power-on instruction is given by a power-on / off signal 12 from a host device (not shown) (FIG. 2A), a power-on signal is given to the power supply 11 from the AND circuit 15 by a power-on / off signal 16 (FIG. 2C). As a result, the power output V _OUT (FIG. 2b) rises with the passage of time and eventually becomes constant. When the constant value is reached, a power-on completion signal 26 (FIG. 2d) is supplied from the power source 11 to the power source control circuit 14, and the power-on is completed. In this case, the first alarm signal (FIG. 2e) and the third alarm signal 21 (FIG. 2f) are at the 0 level assuming that the power supply 11 has no fault.

Here, it is assumed that some trouble has occurred in the power supply 11.
In this case, the alarm signal 17 becomes level 1. That is, an alarm is generated (FIG. 2e). In this state, the on / off signals 12, 16 are kept on. (Fig. 2a,
c). Therefore, the ON / OFF signal 16 of level 1 and the first alarm signal 17 are input to the AND circuit 18, and the second alarm signal 19 also becomes level 1. Since the latch circuit 20 is not operating in this case, the second alarm signal 19 becomes the third alarm signal 21 as it is (FIG. 2f), and the power control circuit 14
Is input to the negative input terminal of the AND circuit 15. This AND circuit
The other input terminal of 15 is a level 1 ON / OFF signal
Since 12 is input, the ON / OFF signal 16, which is the output of the AND circuit 15, becomes level 0 (FIG. 2c). Therefore, the power supply 11 is turned off and its output voltage V _OUT becomes 0 (FIG. 2b).

Next, as described above, the power supply 11 fails, and the power supply 11 is turned off by issuing the alarm signal 17, and thereafter,
A case where the power supply 11 is turned on again from a higher-level device (not shown) will be described.

In this case, the power supply control circuit 14
An ON signal is supplied to one terminal of the AND circuit 15 as the ON / OFF signal 12 (FIG. 2d). In this state, since the first alarm signal 17, and therefore the second alarm signal 19, is at level 1 (FIG. 2e), it cannot be turned on again unless it is released. Therefore, the ON / OFF signal 12 branches and is supplied to the alarm reset signal generation circuit 24. As a result, the alarm reset signal generating circuit 24 supplies the reset signal 25 to the latch circuit 20, and the latch circuit 20 resets the second alarm signal 19 and supplies the third alarm signal 21 of level 0 (the second alarm signal 21). 2f). On the other hand, the AND circuit 15 which has received this signal sends the level 1 ON / OFF signal 16 to the power supply 11 because it receives the ON / OFF signal 12 (FIG. 2c). As a result, the power supply 11 is turned on again, and its output voltage V _OUT rises (FIG. 2b). Then, an input completion signal 26 (FIG. 2d) is sent to the power control circuit 14,
The restart operation is completed.

〔The invention's effect〕

As described above, the power control device of the present invention invalidates the alarm signal when there is no power-on signal, and resets the alarm signal regardless of the power-on signal line when the power is turned on again after the power failure is removed. Accordingly, there is an effect that the influence of the reset pulse generated before the power supply output becomes constant can be removed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a power supply control device according to the present invention, FIG. 2 is an operation timing diagram thereof, FIG. 3 is a block diagram showing a conventional power supply control device, and FIG. It is. 11 Power supply, 18 AND circuit, 20 Latch circuit, 24 Alarm reset signal generation circuit.

Claims (1)

(57) [Claims] 1. A power supply control device for controlling power-on, power-off, abnormality processing, etc. of a power supply used in an information processing device or the like. A power failure signal that outputs a reset signal in response to a power-on signal from a higher-level device when a power supply that has been cut off due to a power failure is restarted, and a reset from the power failure signal reset signal generation circuit And a circuit for resetting the power failure signal by a signal.