JPS6277650A - Information processor equipped with advanced control part - Google Patents

Abstract

PURPOSE:To evade effectively unnecessary job abortion and a system-down state by stopping the execution of an execution part after the execution part enters a retry ready state when trouble occurs to an advanced control part. CONSTITUTION:If a retry flag 23 is set (ready to retry) when an advanced control part trouble display means 11 detects trouble, a high-level signal indicat ing the occurrence of trouble is sent to an execution part operating means 21 through an OR gate 27, an AND gate 28, and an OR gate 29, so that the execution part 2 is stopped immediately from operating. If the retry flag 23 is reset (not ready to retry) and one of flip-flops 251-244 is set when the trouble is detected, the outputs of the OR gate 17 and AND gate 18 are both low in level. Consequently, the trouble is not reported to an execution part operation stopping means 21 and the execution part 2 continues to operate. If the retry flag 23 is set in this state, the execution part 2 is stopped from operating.

Description

DETAILED DESCRIPTION OF THE INVENTION Purpose of the Invention Industrial Field of Application The present invention is used in computer systems and the like. There is a type of system that has a pre-control unit that performs pre-fetch control of operands to speed up processing.

Conventionally, in this type of information processing apparatus, when a failure occurs in the advance control unit, the operation of the entire information processing apparatus is stopped, and the failure is handled according to the execution unit retry information at this point in time.

Problems to be Solved by the Invention In the conventional information processing apparatus described above, when a fault occurs, the entire operation is stopped regardless of the location where the fault occurs, and the fault processing is performed according to the execution unit's try information. There is.

Therefore, even if a failure occurs in the preceding control unit, if the execution unit happens to be in a retry-disabled state at that time, it will be assumed that the execution unit is in a retry-disabled state due to a failure, and the job will be aborted or system down. There is a problem that it becomes .

Means for Solving the Problems The information processing apparatus of the present invention includes a preceding control section failure detection display means, and a preceding control section operation stopping means for stopping the operation of the preceding control section when a failure of the preceding control section is detected. and an execution unit operation stopping unit that continues the operation of the execution unit until it becomes retryable and then stops the execution unit if the execution unit is not in a retryable state at the time when a failure is detected by the advance control unit failure detection display unit. The system is configured to avoid unnecessary job aborts and system downs by providing means for preventing stalls caused by m-continuation of these operations.

Hereinafter, the operation of the present invention will be explained in detail together with examples.

Embodiment FIG. 1 is a block diagram showing the configuration of only the portions of an information processing apparatus according to an embodiment of the present invention that are necessary for explaining this embodiment.

In the figure, 1 is an advance control section, 2 is an execution section, 11 is an advance control section failure detection display means, 12 is an advance control section operation stop means, 2
1 is an execution unit operation stop means, 22 is an execution unit failure detection display unit, 23 is a retry flag, 241 to 244, 251 to
254 is a flip-flop.

The advance control unit 1 prefetches instructions and operands and supplies them to the execution unit 2. The execution unit 2 executes instructions according to the instructions and operands supplied from the 1-preceding control unit 1.

The preceding control section fault detection and display means 11 detects a fault in the preceding control section 1 using a parity check, a duplex collation structure, etc., and displays the detected fault. When a failure is detected, the preceding control section operation stopping means 12 is notified, and the operation of the preceding control section 1 is stopped.

Both the advance control unit 1 and the execution unit 2 are pipelined. In this embodiment, the execution unit 2 is configured with five stages, and updates are performed at the lowest stage. Once this update is performed, the instruction can be retried. In the pre-update retry enabled state, re-execution (retry) is possible starting from the instruction pointed to by the instruction counter.

The retry flag 23 is composed of a flip-flop, and is reset by the output of the flip-flop 254 and reset by the output of the flip-flop 244. Flip-flops 241 to 244 hold reset instructions corresponding to each stage of the pipeline.

At the time when a failure is detected by the preceding control unit failure detection display means 11, the retry flag 23 is set to the cent state (retry possible).
If so, ORGATE 27. A high signal is used to notify the execution unit operation stopping means 21 of the occurrence of a failure via the AND gate 28 and the OR gate 29, and the operation of the execution unit 2 is immediately stopped.

On the other hand, at the time when the failure is detected by the advance control unit failure detection display means 11, the retry flag 23 is in the reset state (retry is not possible) and the cent instruction is held in any of the flip-flops 251 to 254. If so,
The output of the OR gate 27, and hence the output of the Ant gate 28, is low, and the execution unit operation stop means 21 is not notified of the failure, and the execution unit 2 continues to operate.

When the retry flag 23 is set as this operation continues, the OR gate 27. A failure occurrence notification by a high signal is sent to the execution unit operation stop means 21 via the AND gate 28 or gate 29, and the operation of the execution unit 2 is stopped.

FIG. 2 is a time chart illustrating the operation when execution is stopped after waiting for a retry-enabled state.

In this time chart, the flip-flop pair (24i
, 25i) (i=1 to 4) are displayed by a combination of the states of each flip-flop. That is, the flip-flop pair (24i, 25i) is (“1”,
0”) is “R”, (“0”, “1”) and (“
1”, “1”), “S”, (“0”, “’0”)
''), "H" is displayed, respectively.

When a failure in the advance control unit 1 is detected at timing 1.0, the execution unit 2 continues to operate until timing t3.
4 and subsequent operations are stopped.

If no cent instruction is held in the flip-flops 251 to 254, if an attempt is made to continue the operation of the execution unit 2 until the retry flag 23 is set,
This results in a stall condition.

To prevent this stall state, flip-flop 2
When no cent instruction is held in 51 to 254 and the retry flag 23 is in the reset state, the AND gate 2
The configuration is such that the operation of the execution section 2 is stopped by supplying the high signal of No. 6 to the execution section operation stopping means 21 via the AND gate 28 and the OR gate 29.

FIG. 3 is a time chart explaining the operation in this case. A failure in the advance control unit 1 is detected at timing t0, and at this timing, the retry flag 23 is "0" and the flip-flops 251 to 254 are all "0".

Therefore, in the execution unit 2, timing 1. Further operations will be stopped.

After the execution unit 2 stops operating, the failure handling flip-flop is activated, the retry flag 23 is set, and failure handling is performed according to the reset state.

Above, we have illustrated the case where the execution part has a pipeline configuration, but
The present invention is also applicable to a single-stage configuration in which one instruction is executed over multiple clock periods.

Effects of the Invention As explained in detail above, the information processing device of the present invention has the following effects:
When a failure occurs in the advance control section, the execution section is configured to wait until the execution section is ready for retry and then stop its execution, which effectively prevents unnecessary job aborts and system downtime. Ru.

[Brief explanation of drawings]

FIG. 1 shows a block opening, a second
3 are time charts for explaining the operation of the above embodiment. 1. Advance control section, 2. Execution section, 11. Advance control section failure detection display means, 12. Advance control section operation stop means,
21... Execution unit operation stop means, 22... Execution unit failure detection display unit, 23... Retry flag, 241 to 244,
251-254...Flip-flop.

Claims (1)

[Scope of Claims] In an information processing device including a preceding control section upstream of an execution section, there is provided: preceding control section fault detection and display means for detecting and displaying a fault in the preceding control section; and this preceding control section fault detection and display means. advance control unit operation stopping means for stopping the operation of the advance control unit when a failure is detected by the preceding control unit failure detection display means; The preceding control unit is characterized by comprising an execution unit operation stopping means for continuing the operation of the execution unit until it reaches a retryable state and then stopping it, and a means for preventing a stall due to the continuation of this operation. Information processing equipment equipped with.