JPH0528854B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] Regarding a computer system equipped with an engineer panel used for program debugging, the purpose of the engineer panel is to realize various stop conditions and deal with instruction prefetch. The computer system includes an address match detection circuit that detects a match signal when data on the bus matches a predetermined value, and determines whether to validate or suspend the match signal detected by the address match detection circuit. and software means, which determine whether or not a stop condition is satisfied when the match signal of the address match detection circuit is input, and determine whether or not the stop condition is satisfied. A stop condition determining means transfers control to the engineer panel when the stop condition is satisfied, and sets the execution of the program instruction to a single step mode when the stop condition is not satisfied, and sets control of the address coincidence control means to a hold mode. and internal interrupt processing control means for canceling the single step mode and setting the control of the address coincidence control means to a valid mode after the execution of the program instruction is completed.

[Industrial application field]

The present invention relates to a computer system equipped with an engineer panel used for program debugging, and more particularly to a computer system equipped with an engineer panel that can realize various stop conditions and deal with instruction prefetch.

When debugging a computer system program, you can use the engineer panel to stop the computer system at any point during operation and check the contents of memory data, register data, and CPU status at the time of the stop. I'll look into it. The engineer panel used for this purpose needs to be configured so that program debugging can be executed more efficiently.

[Conventional technology]

A conventional technique of an engineer panel control method for transferring control from a computer system to an engineer panel will be described with reference to FIGS. 5 and 6.

As shown in FIG. 5, in a conventional engineer panel 10 connected to a computer system 20 consisting of a CPU 1, memory 2, bus 3, display device 4, keyboard 5, and printer 6, in order to transfer control from the computer system 20, , an address match detection circuit 11 consisting of hardware, a condition match detection circuit 13, and an AND circuit 14 that takes the logical product of the output of the address match detection circuit 11 and the output of the condition match detection circuit 13. There is. This address match detection circuit 11 is
As shown in FIG. 6, the setting address register 11a where the address data for stopping the operation of the computer system 20 is set and the address data flowing on the address bus 3a match the setting address data of the setting address register 11a. and an address match AND gate 11b that operates to send out a match signal when the match occurs. On the other hand, the condition match detection circuit 13 also has the sixth
As shown in the figure, a data address register 13a is used to set a memory address that imposes a condition for stopping the operation of the computer system 20, a memory data register 13b is used to set memory data that becomes a stop condition at that time, and a data Memory data flowing on bus 3b is stored in this memory data register 1.
The data matching AND gate 13c operates to send out a matching signal when matching with the setting memory data of 3b.

In the conventional engineer panel 10 configured as described above, when the address match detection circuit 11 detects a match of address data and the condition match detection circuit 13 detects a match of memory data, an output is sent to the AND circuit 14. is sent out, and the output of this AND circuit 14 becomes the highest priority interrupt signal (NMI signal) for CPU 1, stopping the execution of the program processing of CPU 1, so that control is transferred to the engineer panel. be. Then, the program used the engineer panel 10 to which control was transferred to refer to various states of the computer system 20 and execute debugging of the program.

[Problem to be solved by the invention]

However, according to such conventional technology, when the CPU 1 accesses a specified memory address and the memory data at that time has reached a set value, the computer system 20 is stopped, which is a so-called condition regarding memory data. Although the address stop function can be realized,
Unless a dedicated circuit is provided inside CPU1, the CPU
It was not possible to judge whether the latch data of the register inside the 10000 matched the set value, and to transfer control to the engineer panel 10 if they matched. From this point on, a problem arose in that the efficiency of program debugging was not sufficiently improved.

One way to solve this problem is to omit the hardware condition match detection circuit 13 and issue a top priority interrupt (hereinafter referred to as NMI interrupt) to the CPU 1 when the address match detection circuit 11 detects a match between address data. It is conceivable to take a method in which conditions are set in the internal registers of the CPU 1 and the like is made by executing the software. However, many computer systems 20 employ a so-called prefetch function that fetches an instruction in advance before executing it, and in a computer system 20 that has such a prefetch function, the address match detection circuit 11 simply If you apply an NMI interrupt only by
In the instruction before the original setting address data instruction
An NMI interrupt will be generated. From now on, even if the interrupt is canceled and the process is restarted because the condition is not met, the NMI interrupt will be triggered again by that instruction and the engineer panel 10 will not be able to be configured.

The present invention has been made in view of the above circumstances, and it is an object of the present invention to provide a computer system equipped with a new engineer panel that can realize various stop conditions and deal with instruction prefetch. It is.

[Means to solve the problem]

FIG. 1 is a diagram showing the principle configuration of the present invention.

In the figure, 10 is an engineer panel and 20 is a computer system. Engineer panel 10 is the fifth
Address match detection circuit 1 explained in FIG.
1 and a display means 12 consisting of a plurality of lighting means for displaying the contents of register data and memory data. 21 is an instruction execution means for executing the instructions of the program of the computer system 20; 22 is a single step setting means; the instruction execution means 2
1 is for setting the execution of the instruction to single step mode, and 23 is an address coincidence control means, which is used to enable or suspend the coincidence signal detected by the address coincidence detection circuit 11. The control device 24 is a stop condition determining means, which is constituted by software means, which inputs the coincidence signal of the address coincidence detection circuit 11 via the address coincidence control means 23, and when the input of this coincidence signal is input. 25 is an internal interrupt processing control means for determining whether or not a preset data stop condition is satisfied at a certain time, and 25 is an internal interrupt processing control means for terminating instruction execution in the single step mode of the instruction execution means 21. This is for later executing internal interrupt processing.

[Effect]

In the present invention, the stop condition judgment means 24 transfers control to the engineer panel 10 when it judges that the stop condition is satisfied, and sets the single step setting means 22 when it judges that the stop condition does not hold, and sets the command execution means 22.
The execution of the instruction No. 1 is set to the single step mode, and the control of the address coincidence control means 23 is set to the pending mode. Then, as internal interrupt processing, the internal interrupt processing control means 25 resets the single step setting means 22 to cancel the single step mode, and
Processing is performed to set the control of the address matching control means 23 to the valid mode.

In the present invention, the stop condition determining means 24
When it is determined that the stop condition is not satisfied, processing is performed to instantaneously display the contents of the mismatch information on the display means 12 while continuing execution of the command.

As described above, in the present invention, since the stop condition determining means 24 consisting of software means determines the stop condition, it becomes possible to set the stop condition for things other than memory data.

Further, if the computer system 20 has an instruction prefetch function, the address match detection circuit 11 will detect address match by prefetch before executing an instruction having a stop address.
At this time, for example, the instruction immediately preceding the instruction having the stop address (hereinafter, to simplify the explanation, it is assumed to be the instruction immediately before the instruction) has started execution, so the stop condition determining means 24 performs the following steps. After determining the mismatch between the actual execution address and the address detected by the address match detection circuit 11, the address match control means 23 is set to the hold mode without transferring control to the engineer panel 10, and then the instruction execution mode is changed in a single step. mode and instructs execution of the previous command.

In response to this instruction, the instruction immediately before the instruction having the stop address is executed, and at the end of its execution, the internal interrupt processing control means 25 cancels the single step mode of the instruction execution mode, and After setting the address coincidence control means 23 to the valid mode, restarting from the instruction having the stop address is instructed. When restarted in this way, the stop address flows on the address bus and the address match detection circuit 11 detects an address match, but since the detected address at this time matches the actual execution address, ,
When the stop condition determining means 24 confirms that both addresses match, it determines whether or not other set stop conditions are satisfied, and if so, transfers control to the engineer panel 10. .

In this way, in the present invention, even if the computer system 20 has an instruction prefetch function, it is possible to accurately determine whether the stop condition is met.

Further, in the present invention, since the content of the mismatch information is displayed, debugging processing can be performed extremely efficiently.

〔Example〕

Hereinafter, the present invention will be explained in detail according to Examples.

FIG. 2 shows a system configuration diagram for realizing the present invention. As shown in this figure, a computer system 20 includes a CPU 1, memory 2, bus 3, display device 4, keyboard 5, and printer 6.
The engineer panel 10 of the present invention connected to
Although the address match detection circuit 11 is implemented as in the prior art, the condition match detection circuit 13 is omitted, unlike the prior art. As explained in FIG.
When the address data flowing on the address bus constituting the CPU 1 matches the set address data set in advance by the programmer, the CPU 1
It will operate to generate a match signal that will be the NMI signal to.

12 in the figure is a display means consisting of, for example, eight LED rows, and the engineer panel 1
After control is transferred to 0, the light is turned on to display the contents of the register data of the CPU 1 and the memory data of the memory 2 according to instructions from the programmer. This display means 12 is also equipped with the conventional engineer panel 10, but the fifth
This is omitted in the figure for convenience of explanation.

In the present invention, instead of omitting the condition match detection circuit 13, the CPU 1 is configured to execute a predetermined trap interrupt process for transferring control to the engineer panel 10. Next, according to Figure 3, the contents of this trap interrupt processing executed by CPU1 and the CPU
The contents of the NMI interrupt processing that will be executed by No. 1 will be explained.

Figure 3A is a flowchart of NMI interrupt processing.
FIG. 3B shows a flowchart of trap interrupt processing. As shown in the flowchart of FIG. 3A, when the NMI signal is input from the engineer panel 10, the CPU 1 first performs the following steps in step 10.
Determine whether the stop condition is met.
This stop condition, which is set in advance by the programmer, is different from the conventional method and is not limited to those related to memory data, since the judgment of the present invention is made by software means.
1 register data etc. can also be set. If it is determined in step 10 that the stop condition is met, the process advances to step 11 to transfer control to the engineer panel 10. The engineer panel 10 to which control has been transferred in this way turns on the stop lamp, executes a keyboard operation monitoring routine, accepts keyboard operations from the programmer, and performs an engineer panel operation process for exchanging data with the CPU 1. I will be entering.

On the other hand, if it is determined in step 10 that the stop condition is not satisfied, step 12 is performed.
Then, the match signal input as the NMI signal from the address match detection circuit 11 is released, and a hold process is performed to prevent the reception of subsequent match signals. When this release pending processing is completed, in the next step 13, the program instruction is set to be executed in single step mode, and in the following step 14, processing is performed to return to the program that caused the interrupt.

The trap interrupt process shown in FIG. 3B is executed by an internal interrupt operation when the execution of the program instruction is set to the single step mode at the end of the execution of the program instruction. As shown in Figure 3B, when the single step mode is set, the CPU 1
First, in step 20, it is determined whether the match signal from the address match detection circuit 11 is in a pending state. If it is determined in step 20 that the status is not on hold, step 2
1, and the engineer panel operation process is entered in the same way as the process in step 11. on the other hand,
If it is determined in step 20 that the program instruction is pending, the process proceeds to step 22, where the settings are reset to accept the match signal from the address match detection circuit 11, and in the next step 23, the execution of the program instruction is changed to single-step mode. or cancel it. Then, in the following step 24, processing is performed to return to the program where the interrupt occurred.

Next, we will explain by taking a concrete processing example that by executing the interrupt processing of the present invention, control can be transferred to the engineer panel 10 without any problem even if there is an instruction prefetch function. explain. FIG. 4 shows the instruction steps for this explanation, and it is assumed that address matching is set for this n address instruction.

Since the program prefetches the instruction at address (n-1) when executing the instruction at address (n-1), an address match occurs, and at the end of the instruction at address (n-1), the address match detection circuit 11 of the engineer panel 10 detects A match signal will be sent and an NMI interrupt will occur. Since this match signal is generated when the instruction at address n, for which address match is set, has not yet been executed, step 10
It is determined that the stop condition is not satisfied. Thereafter, in step 12, the match signal from the address match detection circuit 11 is released and the process is placed in a pending state, and in step 13, the single step mode is set, and the process returns to the end of the (n-1) address instruction.

In the conventional case, an infinite loop would be entered by the match signal from the address match detection circuit 11 generated by returning to the (n-1) address instruction, but in the present invention, this match signal is detected by the processing in step 12. Since the instruction is not accepted, the instruction at address n will be executed in single step mode. Then, at the end of this n-address instruction, a trap interrupt is generated.
In this trap interrupt, since the match signal from the address match detection circuit 11 is in a pending state due to the processing at step 12 of the (n-1) address instruction, this match signal will be accepted at step 22. At the same time, in step 23, the single step mode is canceled and the process returns to the point at which the n address instruction ends. Then, the (n+1) address instruction and the (n+2) address instruction are executed successively, and the program returns to the (n-1) address instruction again in accordance with the "LOOP" instruction. Upon execution of the subsequent (n-1) address instruction, a match signal is sent from the address match detection circuit 11 as described above and an NMI interrupt is entered, but this time, since the n address instruction has already been executed, Step 10
When it is determined that the stop condition is met, step 11 is entered and control is transferred to the engineer panel 10.

As described above, in the present invention, the instruction prefetch function is configured to temporarily not accept the match signal from the address match detection circuit 11, execute the instruction in single step mode, and then return to the original state. The inconvenience that would occur if the execution of the command stopped does not occur.

In the present invention, when it is determined in step 10 of the NMI interrupt processing that the stop condition is not met, the display means 12 instantly displays the mismatch information. By displaying the information in this way, the programmer can perform debugging processing more efficiently. The reason for instantaneous display is that if the program is stopped carelessly, the execution conditions may be disrupted.

In addition, in the specific example of Figure 4, “LOOP”
Although the explanation has been shown in which the instruction at address n is changed from unexecuted to executed and the stop condition is satisfied by using the instruction, this is only for the convenience of explanation and is not intended to explain the operation of the present invention. It is not limited.

〔Effect of the invention〕

As explained above, according to the present invention, since the judgment of condition matching is made by software means of the CPU, in addition to memory data, for example, internal data, IO port data, current memory space number, etc.
In addition to being able to set arbitrary stop conditions for many items such as calculated values of various data,
Even if there is an instruction prefetch function, it becomes possible to implement this condition matching judgment. Therefore, debugging the program becomes easier.

Furthermore, according to the present invention, the internal processing status of the program can be easily recognized by an external operator while the program is running, making it possible to improve the efficiency of programs that are difficult to control when the program is stopped. This makes it possible to provide a high quality program development environment.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a system configuration diagram of the present invention, FIG. 3 is a flowchart of interrupt processing executed by the present invention, and FIG. 4 is a diagram for explaining the operation of the present invention. Instruction step diagram, Figure 5 is a system configuration diagram of the conventional technology, and Figure 6 is a diagram of the conventional technology.
FIG. 3 is a hardware configuration diagram for generating an NMI signal. In the figure, 1 is the CPU 1, 2 is the memory, 3 is the bus,
10 is an engineer panel, 11 is an address match detection circuit, 12 is a display means, 13 is a condition match detection circuit, and 20 is a computer system.

Claims (1)

[Scope of Claims] 1. In a computer system 20 including an engineer panel 10 for debugging a program, the engineer panel 10 detects a match when data on an address bus matches a predetermined value set in advance. The computer system 20 includes an address coincidence detection circuit 11 that detects a signal, and the computer system 20 includes an address coincidence control means that controls whether the coincidence signal detected by the address coincidence detection circuit 11 is enabled or suspended. 23, which is configured by software means and determines whether or not a preset data stop condition is satisfied when the match signal of the address match detection circuit 11 is inputted via the address match control means 23. If the stop condition is satisfied, the engineer panel 10
a stop condition determining means 24 which transfers control to the stop condition, sets the execution of the program instruction to single step mode when the stop condition is not satisfied, and sets the control of the address coincidence control means 23 to a hold mode; After the execution is completed, when the execution of the program instruction is set to the single step mode, the internal interrupt processing control means 25 cancels the single step mode and sets the control of the address coincidence control means 23 to the valid mode. A computer system equipped with an engineer panel characterized by: 2. In the computer system comprising the engineer panel according to claim 1, the stop condition determining means 2
4. A computer system equipped with an engineer panel, characterized in that when the computer system 4 determines that a stop condition is not met, content of discrepancy information is instantaneously displayed on a display means 12 provided on the engineer panel 10.