JPS6273760A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device, and particularly relates to a bulk semiconductor device (EMO8).
The present invention relates to a semiconductor device suitable for use in an output cover-to-circuit, particularly for prevention of latch-up phenomena.

[Technical head of the invention and problems with the background technology] This type of 0MO8 is often provided with a guard ring. The guard ring is a diffusion region formed to surround the FET, and is a part of the original FET. It is not involved in the operation, but is intended to sink external noise current so that the noise current does not forward bias the junction between the diffusion layer of the FET and the substrate on which the FET is placed. Examples of guard ring configurations are shown in FIG. 5 J5 and FIG. N, P).

When a voltage greater than the power supply voltage VDD is applied to the output terminal Vout, the diffusion layer of the P-type FET is forward biased, and a noise current is injected, the guard link 2 operates as follows. First, most of the injected holes flow into the P-type substrate St, while the - part passes through the N-well 1 and becomes a base current that recombines with electrons from the N-type guard ring 2. The holes that flowed into the P-type fukari S flow to the ground potential via the P-type gart ring 5, and the N! Sl! F [Ground potential contact l~
It is divided into those that flow from. If there were no P-type girls 1 to 5, all the holes flowing into the substrate S would pass under the N-type FET, pushing up the substrate potential directly under the N-type FET. The P-type gart ring 5 prevents this and contributes to improving the launch-up resistance. The current sunk from the Gart ring 2 on the well 1 side is determined by the increase rate of the vertical parasitic bipolar transistor with the P-type FET diffusion layer as the emitter and the P-type substrate S as the collector. The ratio of the current flowing through the well gart ring, that is, the base current, to the current flowing to the mold substrate S, ie, the collector current, is usually as small as 1/10 to 1/100. Therefore, a guard ring having a conductivity type different from that of the base body is sometimes created.

Examples of configurations of such guard rings are shown in FIGS. 7 and 8. In this case, the guard ring 8 using the P type diffusion layer in the N-well 1 is biased to the ground potential, and the guard ring 10 using the N type diffusion layer on the substrate S is biased to about VDDlf. In this case, when the output terminal becomes larger than VDDJ and a noise current is injected, it is expected that most of the injected noise current will flow to the ground potential using the guard ring 8 of the L1 as a collector. However, with this guard ring configuration, the holes that flow into the substrate with the PM substrate as the collector are not sunk from the N-type guard ring on the substrate S side, but instead flow to the ground potential contact of the substrate S, which was expected. It's not as effective as Song Dynasty. Since the guard ring 10 of the substrate S is reverse biased, the substrate S
The hole in the middle that becomes the rear hole is the board guard ring 1.
It is not out of 0. Moreover, well guard ring 8
P 32F [distance from the junction depth of N-well 1 is 2! , if it is about x or more''2 (this is the case in most actual patterns and is referred to as 11), the odd bipolar whose collector is y, 1 and S is the collector of the guard ring. Since the emitter arrival rate is higher than that of the strange bipolar type, the noise current sunk from the guard ring (which is much more innocuous) is currently used rather than the configurations shown in Figures 7 and 8. Figure 5,
The configuration shown in FIG. 6 is used.

[Purpose of the invention]

An object of the present invention is to increase the sink current due to the guard ring.

[Summary of the invention]

The semiconductor device of the present invention includes, on a surface of a substrate or a well, a diffusion layer of a conductivity type opposite to that of the substrate or the well;
The plate or the diffusion layer and the diffusion layer of the same conductivity type are in contact with each other, and the diffusion layer of the opposite conductivity type is closer to the FET formed in the substrate or the well than the diffusion layer of the same conductivity type. A metal layer is formed to contact and connect both surfaces of the opposite and same conductivity type diffusion layers, which are formed close to each other and in contact with each other. It is characterized in that the same potential as that of the single plate or the above-mentioned tube is applied.

[Embodiments of the invention]

FIGS. 1 and 2 show an embodiment of the present invention.

As shown in the figure, the guard ring of the present invention is arranged such that diffusion layers of different conductivity types are in contact with each other.

The guard ring of the well 1 has a diffusion layer 12 of the opposite conductivity type to that of the well 1, and a diffusion layer 12 of the same conductivity type as the well 1.
3J: formed close to the FET formed in well 1.

On the other hand, the guard ring of the substrate S is formed so that the diffusion layer 14 of the conductivity type opposite to that of the substrate S is closer to the FET formed in the substrate S than the diffusion layer 15 of the same conductivity type as the substrate S. has been done.

Further, in the illustrated embodiment, the well 1 or the substrate S
The diffusion layers 12J3 and 14 of the opposite conductivity type have a smaller surface area than the diffusion layers 13 and 15 of the same conductivity type.

Further, a metal layer 16.17 is provided which contacts both of the diffusion layers 12J3 and 13 or 14 and 15 of different conductivity types formed in contact with each other and electrically connects them, which constitutes the guard ring. . These metal layers 1
6 and 17 are guard rings in the illustrated example)
0 and discontinuously formed, but 1J and 1: 1 and 1 are formed in quick succession. The metal layers 1G and 17 have the same potentials VDDJ9 and VS as those of the metal layer 1 and the substrate S, respectively.
S is applied.

FIG. 3 schematically shows the behavior of the carrier near the guard ring. However, it is assumed that the guard ring is in a completely 70-ting state. In reality, the guard ring diffusion layer is connected to VDD and almost no electron current flows through a well such as J'3D, but the worst case is assumed. The current Δ is the collector current of a strange bipolar with 1] one substrate S] collector and 4,
The famous current C is the collector current of a parasitic bipolar whose collector is the diffusion layer 12 of the guard ring, and the current B is the current A and C.
is the base current associated with . The current flow is an electron current that flows because the current C is recombined at the junction surface of the diffusion layers 12 and 13 or the metal layer 16.

Even if the guard ring is in a floating state in this way, the current flowing through the N-well 1 - N diffusion layer 13 - metal body 16 - P diffusion layer 12 causes the P diffusion layer 12 of the guard ring, which becomes the collector, to be almost equal to VDD. So,
The current C never decreases by 1. That is, to the P-base substrate [
N-well 1 which brings about the potential upper back directly under the N-type FET.
Sync the minority carriers in the middle to make them majority carriers, and P
This prevents it from flowing to the Ei board S.

FIG. 4 shows the behavior of carriers when the surface metal body 16 is directly connected to the VDD potential by wiring. In this case, a part of the base current is supplied from the N-type diffusion layer 13 of the guard ring, but other points are the same as described in FIG. 3.

Although the above description has been made for the case where the substrate S is of the P type, the same applies to the case where the substrate S is of the N type, so a detailed explanation will be omitted.

〔Effect of the invention〕

As described above, according to the present invention, the sink current due to the guard ring can be increased. Therefore, the latch-up durability of the output buffer etc. can be improved.

[Brief explanation of drawings]

FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention, FIG. 2 is a schematic N cross-sectional view of the device in FIG. 1, and FIGS. 3 and 4 are guard rings. 5 to 8 are a plan view 43 and a cross-sectional view of a conventional semiconductor device. S...Substrate, 1...N-well, 3...P type F
rET source/drain, 4...P-type FET gate 1-16...N-type FET source/drain, 7.
...N-type FET gate, 12...P+ diffusion layer of N-well guard ring, 13...N+- diffusion layer of N-well guard ring, '14...N of substrate guard ring
+ expansion rl1 layer, 15...Pl- diffusion layer of substrate guard ring, 16.17... metal layer. Applicant's agent Fi Fuji - Rejection Figure 1A Figure 3

Claims (1)

[Claims] 1. A well of a conductivity type opposite to the first conductivity type is formed at a predetermined depth in a substrate of a first conductivity type, and a well is formed at a predetermined depth on a substrate of a first conductivity type. A semiconductor device comprising a phase correction type FET having a channel of a conductivity type opposite to that of the substrate and the well, respectively, formed on the surface of the well of the second conductivity type, wherein the substrate or the well has a channel of the opposite conductivity type. Alternatively, a diffusion layer of a conductivity type opposite to that of the well and a diffusion layer of the same conductivity type as the substrate or the diffusion layer are in contact with each other, and the diffusion layer of the opposite conductivity type is a diffusion layer of the same conductivity type. The diffusion layer is formed closer to the FET formed in the substrate or the well than the FET layer, and is formed so as to be in contact with each other, and is in contact with the surfaces of both the opposite and same conductivity type diffusion layers to connect them to each other. A semiconductor device characterized in that a metal layer is formed, and the same potential as that of the substrate or the well is applied to the metal layer. 2. In the device according to claim 1, the diffusion layers of opposite and same conductivity types that are in contact with each other are
A device characterized in that the device is disposed on a current path when an SCR is turned on, which is formed between a diffusion layer of a FET of a conductivity type and a diffusion layer of a second conductivity type. 3. The semiconductor device according to claim 1, wherein the diffusion layer of the opposite conductivity type has a smaller surface area than the diffusion layer of the same conductivity type.