JPH04113629A - Semiconductor device - Google Patents

Abstract

PURPOSE:To prevent an electric current from flowing to a semiconductor substrate and to prevent a parasitic PNP transistor from being generated by a method wherein an equivalent circuit is realized also in a saturation region. CONSTITUTION:An N-type diffusion layer 3 which is biased to an N-type diffusion layer 1 is formed in the diffusion layer 1 ; an electrode 7 is formed in an opening 12 in an insulating layer 8 on it; a P-type diffusion layer 2 is formed in a P-type diffusion layer 2 is formed in a biased region inside a chip. An electrode 6 is formed in an opening 11 in the insulating layer 8 on it; it is used as a base. An N-type diffusion layer 3'' to be used as an emitter is formed inside the P-type diffusion layer 2; an N-type diffusion layer 3'' to be used as a collector is formed so as to surround the diffusion layer 3''. Electrodes 5, 6 are formed in openings 10, 11 in the insulating layer 8; a metal electrode 4 which has been connected to the diffusion layer 2 and which is used as a base is formed in an opening 9. Since the N-type diffusion layer 1 is biased at a maximum potential by means of the electrode 7, a parasitic PNP transistor with reference to a substrate 40 is not generated in a saturation region.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and more particularly to an integrated circuit board having a bipolar NPN (NPN) transistor structure.

[Conventional technology]

Conventionally, this type of semiconductor device has the structure shown in FIGS. 3 and 4, and its equivalent circuit is shown in FIG. 5 for the active region and FIG. 6 for the saturated region. That is, in FIGS. 3 to 6, an N-type diffusion layer 3 serving as a collector electrode and a P-type diffusion layer 2 serving as a base are provided on an N-type diffusion layer 1, and an emitter is formed in the P-type diffusion layer 2. N-type diffusion layer 3
', and was insulated from other regions by the P-type wave diffusion layer 20 connected to the substrate 40. Note that the N-type diffusion layer l is formed in the P-type semiconductor substrate 40, and its lower part is the N-type buried layer 30.
is formed.

Further, an insulating layer 8 is formed on the surface, and an opening 12 thereof;
A collector metal electrode 7, a base metal electrode 4, and an emitter metal electrode 5 are formed at 10 and 9, respectively.

In FIG. 5, the transistor 100 of FIGS. 3 and 4 is shown in the non-saturation region, and when saturated, the base of the transistor 100 becomes the emitter, the collector becomes the base, and the ground becomes the collector. A parasitic pnP) transistor 200 is generated.

[Problem to be solved by the invention]

When the conventional semiconductor device mentioned above is used in the saturation region,
As shown in FIG. 6, the equivalent circuit is as follows:
There is a drawback that the transistor 200 is generated and current flows to the substrate (SUB).

The purpose of the present invention is to eliminate such drawbacks and to eliminate parasitic PNPs.
) An object of the present invention is to provide a semiconductor device in which transistors are not generated.

[Means to solve the problem]

The structure of the semiconductor device of the present invention is such that a first region of a second conductivity type serving as a back gate electrode and a second region serving as a base are provided in a diffusion layer of a first conductivity type on a semiconductor substrate; A third region serving as an emitter and a fourth region serving as a collector are provided within the second region, and the third region is surrounded by the fourth region in a donut shape.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

1 and 2 are a plan view and a sectional view of a semiconductor device according to an embodiment of the present invention. In FIG. 1, in this embodiment, an N-type diffusion layer 3 is provided in an N-type diffusion layer 1 for biasing this diffusion layer 1, an opening 12 is provided in an insulating layer 8 thereon, and an electrode 7 is provided. , a region biased at the highest potential within the chip is provided, a P-type diffusion layer 2 is formed, and an opening 1 is formed in the insulating layer 8 above it.
1 is provided, an electrode 6 is provided through this as a base, and P
An N-type diffusion layer 3'' serving as an emitter and an N-type diffusion layer 3'' serving as a collector surrounding the diffusion layer 3'' in a donut shape are formed in the type diffusion layer 2, and openings 10 and 11 are formed in the insulating layer 8, respectively.
and electrodes 5 and 6 are provided. Diffusion layer 2 through opening 9
A base metal electrode 4 connected to the base metal electrode 4 is formed. In the diffusion layer 2 which is the base, there is an N-type diffusion layer 3'' which is the emitter and an N-type diffusion layer 3 which is the collector and surrounds the emitter in a donut shape.
'', and the N-type diffusion layer l is biased at the highest potential by the electrode 7, so in the saturation region, the sixth
A parasitic PNP transistor to the substrate 40 as shown in the figure does not occur. Furthermore, since the emitter is surrounded by the collector in a donut shape, the number of opposing surfaces of the collector and the emitter in four directions is sufficient, so that the current amplification factor hFE becomes large.

〔Effect of the invention〕

As explained above, the present invention is particularly effective in realizing the equivalent circuit shown in FIG. 5 even in the saturation region, and in preventing current from flowing through the semiconductor substrate. Furthermore, compared to the conventional vertical type NPN transistor, the present invention
Since it is a lateral type NPN) transistor, no parasitic PNP) transistor is generated even if the transistor is used in the forward or reverse direction, making it ideal for bidirectional switch circuits. Since the hyt is determined by the facing surface of the collector, the present invention has the effect that a sufficiently large hyt can be provided because the emitter is surrounded by the collector in a donut shape.

Figure 2 is a cross-sectional view of the first silkworm along the line x-x';
4 are a plan view and a sectional view, respectively, of a conventional semiconductor device, FIG. 5 is an equivalent circuit diagram of the active state of FIG. 3, and FIG.
The figure is an equivalent circuit diagram of the saturated state shown in FIG.

■...N-type diffusion layer, 2...P-type diffusion layer, 3
...N-type diffusion layer, 4,5,6.7...Metal electrode, 8...Insulating layer, 9,10,11.12...Mark/opening, 100... ...NPN) transistor, 20
0. Old... Parasitic PNP) transistor, 20. River... P-type diffused layer, 3o... N-type buried layer, 40...
P-type semiconductor substrate.

Agent: Patent Attorney Susumu Uchihara

[Brief explanation of drawings]

Claims (1)

[Claims] A first region of a second conductivity type that becomes an electrode of a back gate and a second region that becomes a base are provided in a diffusion layer of a first conductivity type on a semiconductor substrate, and an emitter and an emitter are provided in this second region. a third region that is a collector and a fourth region that is a collector;
A semiconductor device characterized in that the region is surrounded by a fourth region in a donut shape.