JPS6393154A - Semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a lateral type transistor having a high current amplification factor and excellent noise characteristics by specifying the effective base width of the transistor in a bulk at all times. CONSTITUTION:An N-type epitaxial layer 3 is formed onto a P-type silicon substrate 1, an N-type high-concentration buried region 2 is shaped between these substrate 1 and the layer 3, and a P-type emitter region 11 and P-type collector regions 12 separated in the lateral direction from the P-type emitter region 11 are formed onto the region 2. Consequently, the emitter region 11 and the collector regions 12 are separated in the lateral direction, shaped onto the N-type buried layer 2 and pushed up to the surface of the substrate. Accordingly, carriers injected from the emitter region are not conducted on the surface of the substarte, conducted in the substrate, and are not affected by an interface level distributing on the surface of the substrate, thus acquiring a high amplification factor, then also improving noise characteristics largely. q.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a lateral transistor, and particularly relates to a current amplification factor (
Hereinafter, it will be referred to as hFI. ) and has excellent noise characteristics.

[Conventional technology]

NPN) transistors and PN in bipolar integrated circuits
P) Mixed use of transistors has advantages such as increased freedom in design and simplification of circuit configuration. A horizontal PNP transistor is an easily introduced PNP transistor. usually,
This horizontal PNP transistor is made by simultaneously forming an emitter region 4 and a collector region 5, as shown in FIG. 2, a schematic cross section of which is shown in FIG. There is.

[Problem that the invention seeks to solve]

In the lateral transistor shown in FIG. 2, most of the carriers injected from the emitter region 4 are conducted through the substrate surface and flow into the collector region 5. Many interface states exist on the substrate surface due to the thermal strain layer and the uneven distribution of impurities.

Such an interface level promotes trapping, re-emission, and recombination of carriers conducted on the substrate surface, increases the pace current, and causes a decrease in hFI. Another drawback is that it causes fluctuations in the collector current, deteriorating the noise characteristics.

[Means for solving problems]

The present invention aims to eliminate such drawbacks.

The next carriers injected from the carrier region do not conduct through the substrate surface,
This is an improved version that allows conduction inside the substrate. That is,
The present invention has an emitter region and a collector region formed such that the effective width of the transistor is always defined within the bulk.

〔Example〕

The present invention will be described below with reference to the drawings.

FIG. 1 is a schematic cross-sectional view of an embodiment of a lateral PNP transistor according to the present invention. The same parts as in the conventional example shown in FIG. 2 are given the same numbers.

In this embodiment, an emitter region 11 and a collector region 12 are formed on an N-type buried layer 2 and are spaced apart in the lateral direction.
It rises to the surface of the board.

〔Effect of the invention〕

As described above, in the present invention, the effective width of the transistor is always defined within the bulk.

Therefore, carriers injected from the emitter region do not conduct through the substrate surface, but conduct inside the substrate, and are not affected by the interface states distributed on the substrate surface, compared to conventional lateral PNP transistors. As a result, high hFE can be obtained, and noise characteristics can also be significantly improved.

Note that the present invention is not limited to the above embodiments, and even if the polarity is changed, the scope of the present invention does not depart from the scope of the present invention.

[Brief explanation of the drawing]

FIG. 1 is a schematic sectional view showing an embodiment of a semiconductor device according to the present invention, and FIG. 2 is a schematic sectional view showing an example of a conventional semiconductor device. 1... P-type silicon substrate, 2... N-type high yielding buried region, 3... N-type epitaxial layer, 4... Second-generation emitter Area, 5...P
Type collector region, 6...N-type pace electrode extraction region, 7...Silicon oxide film, 8...
Emitter electrode, 9... Collector electrode, 10...
... Base electrode, 11 ... P type emitter region, 12 ... P type collector region.

Claims (1)

[Claims] a semiconductor layer of an opposite conductivity type formed on a semiconductor substrate of one conductivity type; a first region of the opposite conductivity type embedded between the semiconductor layer and the semiconductor substrate; and a first region of the opposite conductivity type. a second region of the one conductivity type formed on the first region; and a third region of the one conductivity type formed on the first region and spaced laterally from the second region. The semiconductor device is characterized in that upper portions of the second region and the third region reach the surface of the semiconductor layer.