JPS6266675A - Mos type semiconductor device - Google Patents

Abstract

PURPOSE:To improve saturating characteristic and to readily form an ultrafine channel by forming a channel doped region which arrives at a low specific resistance substrate in an inverted wedge shape in the channel. CONSTITUTION:A P<-> type layer 11 is epitaxially grown on a P<+> type low specific resistance substrate 10 to form a substrate 1. In this case, B is doped in the layer 11 to form a channel doped region 71 which arrives at the substrate 10 in an inverted wedge shape. Then, an insulating film SiO2 film is laminated on the surface, a gate 3 is further laminated, and with the gate 3 as a mask a source 4 and a drain 5 are formed by implanting arsenic, thereby forming an MOS semiconductor device. The resistance from the channel of the surface to the substrate is reduced by the shape of the region 71 to readily discharge holes generated by avalanche to suppress a potential rise and to suppress the expansion of a drain depleted layer toward the source in the substrate, thereby enhancing saturating characteristic of a drain current. The channel length is specified by the region 71 of this shape to readily form an ultrafine channel.

Description

[Detailed description of the invention] Industrial applications The present invention relates to a MOS type semiconductor device.

BACKGROUND OF THE INVENTION The miniaturization of MOS type semiconductors has been supported by advances in photolithography. In fact, shortening of the channel length has been achieved by reducing the width of the gate pattern. However, research is also being conducted into using other means to shorten the time even further. Focused Io A
An example of this is channel formation by nB@am (hereinafter abbreviated as FIB) [Japanese Journal
Op Applied Physics (Japanese)
Journal of Applied Physics
s) Vol, 23(j984)L543,). A sectional view thereof is shown in FIG. B (boron) was injected between the lease 4 and the drain 5 without a mask to form a door region 7.

The boron beam diameter is approximately 0.2 μm, and the dose is lX10
"Cl11E-2.The width of door area 7, that is, B
This is an attempt to define the effective channel length using the distribution of .

Problems to be Solved by the Invention The above conventional example is an effective means of forming a short channel, but the holes generated by the 7-balance near the drain are P+
Since it is sucked into the region 7 and increases the potential there, positive feedback occurs in which the drain current increases.

Therefore, the drain resistance rp (3avD/θ
There was a practical problem that ID) was small and the gain of the amplifier was low (in a logic circuit, the inverter waveform shaping ability was low).

An object of the present invention is to provide an MO8 type semiconductor device with a fine channel length and high saturation characteristics.

, Means for Solving the Problems In the present invention, as a means for solving the above-mentioned problems, an inverted wedge-shaped channel doped region is provided in the channel and reaches the low resistivity substrate.

Effect: This inverted wedge-shaped channel doped region has zero near the surface.
．． Even if it is as thin as 1 to 0.2 μm, it is wide inside the board, so
The resistance from the surface channel to the substrate is small, making it possible to
Holes generated by shearing are easily discharged. That is, potential rise in the channel doped region is suppressed.

Further, due to the shape, expansion of the drain depletion layer in the substrate toward the source, that is, punch-through is suppressed. From both of these aspects, the saturation characteristics of the drain current are improved. .

explain. FIG. 1 is a sectional view of a first embodiment of the device of the present invention.

A P layer 11 is epitaxially grown on the door substrate 10 to form the substrate 1. For this purpose, vapor phase growth method using thermal decomposition of silane SiH4 and molecular beam epitaxy/I/technology (
M B E =Moleculax Beam Epit
axiaj technology) is used, but
At this time, B is selectively doped at a desired position by FIB to form an inverted wedge-shaped channel doped region 71 (selective doped epi-growth: 31st Applied Physics Conference (1984) Proceedings P, eeo.

Miyauchi et al.).

The surface is thermally oxidized to grow a 10 nm thick SiO□ film 2, and a polysilicon gate 3 is formed thereon. The n-layer type source 4 and drain 5 are formed by arsenic implantation (dose 3 x 10" tx-2) using the gate 3 as a mask. At this time, the gate 3 becomes an n-layer type. Note that the third layer 6 is the source - A region for relaxing the electric field between the drain and channel doped regions, formed by arsenic implantation (dose 1012 to 10" cm-2) before gate formation.

Effective channel length Leff Id, as shown,
It is defined by the width at the 5t-1102 interface of the channel doped region. Since this L@ff can be made to be about the minimum beam diameter of FIB, it is possible to achieve a fineness of 0.1 μ, which is difficult to achieve with the current photolithography method.

The impurity concentration of the channel doped region 71 is determined by the threshold near the surface, but in order to lower the resistance inside the substrate, it is better to dope it to a high concentration to a value allowed by the manufacturing method.

FIG. 2 shows another embodiment of the invention. The difference from FIG. 1 is that the inverted wedge-shaped channel doped region does not reach the surface, but is separated by a distance tab.

Even in this case, the threshold value Vt>o, that is, the enhancement type can be used. This is due to the direction in which the work function difference φMS between the gate 3 and the substrate depletes the substrate surface (%s > O for n-channel, φMs < O for P-channel).
If , the channel thickness t. The concentrations of the h and n layers may be set appropriately. If Fig. 1 is a surface channel type, the second
The figure corresponds to a so-called buried channel type. Note that the P+ substrate 10 referred to here refers to a part of the substrate, for example, a complementary MOS
It may also be one diffusion layer selectively formed on the bottom of the P-well.

Effects of the Invention As described above, in the present invention, since the channel length is defined by the inverted wedge-shaped channel doped region, it is easy to form a fine channel, and the resistance from the a-channel region to the inside of the substrate is low. Since the potential rise in the channel doped region is small and the width of the channel doped region is wide inside the b-substrate, punch-through between the drain and source within the substrate is difficult to occur, resulting in excellent saturation characteristics (drain resistance is low). expensive). This is an important effect for the construction of high-sensitivity amplifiers and pulse waveform shaping circuits in high-density, large-scale integrated circuits.

Another feature of the present invention is that such an effect is not accompanied by an increase in the appearance of the source/drain diffusion layer.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a MOS type semiconductor device according to an embodiment of the present invention, FIG. 2 is a cross-sectional view of another embodiment of the present invention, and FIG.
The figure is a sectional view of a conventional example. 10...Door substrate, 11...P-epitaxial layer, 2...Sio2.3...-
Gate, 4, 6... Source/drain, e...
. . . n layer, 71 . . . channel doped region.

Claims (1)

[Claims] a semiconductor substrate of one conductivity type, at least a part of which is a low resistivity layer; a gate provided on the surface of the substrate via a gate insulating film; and a source/drain of two conductivity types formed at both ends of the gate. , a biconductivity type low concentration layer for connecting the source and drain, and an inverted wedge shape whose width decreases as it approaches the surface, extending from the surface or the vicinity to the depth where it contacts the low resistivity layer. A MOS type semiconductor device comprising a high concentration region of one conductivity type formed and located between the lease and drain.