JP3221901B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device constituting an insulated gate transistor.

[0002]

2. Description of the Related Art Conventionally, an insulated gate transistor has been widely used as an element constituting a large-scale integrated circuit (hereinafter referred to as LSI). Insulated gate type refers to metallic (polycrystalline silicon (Si) made of metal or metal
MIS (Metal I / O) is a general term for a type in which a voltage is applied to an electrode of a MIS (Metal I / O) and the semiconductor surface is controlled via an insulator.
nsulator Semiconductor). Among them, those using an oxide film as an insulator are MOS (Metal Oxide Se
MNS (Metal Ni)
tride Semiconductor), M using alumina coating
It corresponds to AS (Metal Alumina Semiconductor).

FIG. 15 shows an electron conduction type (hereinafter referred to as n) as an example.
It is called a channel. 1) shows the structure of the MOSFET.

Referring to FIG. 1, reference numeral 601 denotes a p-type silicon substrate, and n ⁺ source regions 602 and n
^{A +} drain region 603 is formed, a gate oxide film 604 as the insulator is formed on the channel formation region, and a gate electrode 605 as the metal electrode is formed on the gate oxide film 604. .

In such a structure, the gate electrode 60
When a + voltage is applied to 5, an electron is attracted to the surface side in a region below the gate oxide film 604 in the substrate 601 to form an n-type channel which serves as a carrier, and current flows through this channel. It is possible to flow from the source region 602 to the drain region 603.

In addition, such MISFETs as MOS, etc.
In recent years, SOI (Semiconductor on Insul
ator) structure is often used. This SOIMOSFET
Is a technology in which a new element is constructed on an insulating film, which is indispensable for realizing high-density and high-performance elements such as three-dimensional integrated circuits. This is one of the important technologies that enables complete separation of individual elements even in an integrated circuit having the same configuration as that of the above.

FIG. 16 shows an example of the structure of an n-channel MOSFET having an SOI structure.

In this figure, reference numeral 701 denotes a p-type silicon substrate, on which an interlayer isolation oxide film layer 702 for electrically insulating and separating the upper and lower layers to provide the SOI structure is formed. The part is the oxide film layer 70
2 is formed. Reference numeral 703 denotes the n + -type source region, 704 denotes an n + -type drain region, 705 denotes a gate oxide film, and 706 denotes a gate electrode. A semiconductor region on the oxide film 702 except for the source region 703 and the drain region 704 is a channel formation layer 707 that forms a channel between the two.

The basic operation is the same as that shown in FIG. 15, but because of the presence of oxide film 702,
Even when the impurity concentration of the upper silicon layer (that is, the channel formation layer 707) is reduced, the depletion layer extends from the source region 703 and the drain region 704, so that the source and the drain are electrically connected. Punch-through phenomenon)
Is suppressed. Therefore, the impurity concentration of the channel formation layer 707 can be reduced, so that the impurity scattering there is reduced and the vertical electric field unique to the MIS transistor is also reduced, so that the current value flowing from the source region 703 to the drain region 704 is reduced. Will increase. Also,
Since the oxide film 702 exists, the upper element portion and the base substrate 701
And small parasitic capacitance. Further, since the oxide film 702 is insulated from the base substrate 701, the base substrate 7
01, the charge generated by the radiation does not affect the operation as the nMIS transistor.

[0010]

However, in the MIS transistor and the SOI type MIS transistor described above, the main conduction carriers have high energy due to the high electric field generated at the junction between the drain region and the channel region. There is a problem in that the ion is accelerated to cause collision ionization, and the charge generated due to this, which has a polarity opposite to that of the main conduction carrier, adversely affects the characteristics of the transistor.

For example, in the case of the above-mentioned n-channel transistor, holes are generated by impact ionization in the vicinity of the drain region. These holes are easily injected into the gate insulating film, and the quality of the gate insulating film is reduced. This causes the transistor characteristics to fluctuate. In a hole conduction type pMIS transistor and an SOI type pMIS transistor, electrons generated by impact ionization have similar adverse effects on characteristics.

Even if a gate voltage is applied until an inversion layer is formed in the channel forming layer, an electrically neutral region exists in the channel forming layer.

FIG. 17 shows this state in the case of an SOI type nMIS transistor.

In FIG. 1, reference numeral 801 denotes an upper and lower interlayer insulating oxide film formed on a p-type base substrate (not shown);
2 is an n + type source region, 803 is an n + type drain region,
Reference numeral 804 denotes a gate oxide film, 805 denotes a gate electrode, 806 denotes a channel forming layer, and solid lines in the cross section of the element are equipotential lines formed by connecting portions of the same potential. ing.

As shown in the figure, even if the SOI type is used, if the channel forming layer 806 becomes thicker, the depletion layer becomes the channel forming layer 806 even when a gate voltage is applied to the level at which the inversion layer is formed.
The channel formation layer 806 does not reach the lower oxide film 801.
An electrically neutral region (shaded portion) remains therein. Therefore, holes generated by the impact ionization flow below the channel having a low potential, so that holes are accumulated in a neutral region generated in the channel formation layer 806, and the potential of the channel formation layer 806 is increased.

For example, the thickness TSOI of the channel formation layer is 2
500 Å, same impurity concentration CSOI = 10 ¹⁷
At cm ^-3 and V D = VG = 1.5 V, the hole concentration in the hatched portion shown in FIG. 17 is higher by two to three orders of magnitude than that around it, and reaches 10 ¹⁴ cm ^-3 . As a result, the same effect as when a positive voltage is applied to the underlying substrate occurs, and the current-
As in the case of the voltage characteristics, a kink occurs at a drain voltage at which holes start to accumulate, and a flat saturation region cannot be formed when the drain voltage is further increased. Therefore, there is a problem that stable circuit operation cannot be guaranteed.

The present invention has been made in view of the above-mentioned problems of the prior art, and it is an object of the present invention to provide a charge (hole (n-channel) or electron) having a polarity opposite to that of a carrier generated by impact ionization. It is an object of the present invention to provide a semiconductor device forming a MIS transistor which prevents (p-channel)) from entering a gate oxide film and accumulation in a channel formation layer, and thus has high reliability with less fluctuation in characteristics.

[0018]

A semiconductor device according to the present invention comprises: a semiconductor substrate; an insulating separation layer formed on the semiconductor substrate; a SiGe layer formed on the insulating separation layer; A first conductivity type silicon region formed in the silicon region, a second conductivity type source region and a drain region formed separately from each other in the silicon region, and the silicon region surface portion between the source region and the drain region , A gate insulating film formed on the channel region, and a gate electrode formed on the gate insulating film.

It is preferable that the SiGe layer is a layer that is in an energy state in which a carrier having a charge having a polarity opposite to that of a main conduction carrier that conducts in the channel region is drawn.

It is preferable that the SiGe layer includes a first layer in which the composition ratio of Si and Ge is substantially constant.

Preferably, the SiGe layer includes a second layer in which the concentration of Ge increases from zero as the distance from the interface with the silicon region increases.

It is preferable that the first layer is a constant energy layer having a constant energy state over the entire area.

It is preferable that the second layer is a transition layer in an energy state in which the carriers are accelerated.

In particular, in the SOI type MIS transistor, the impurity concentration of the channel forming layer on the isolation oxide film can be lower than that of the MIS transistor having the normal structure without the SOI structure. Electrons or holes easily diffuse in a direction away from the gate insulating film. Therefore, higher reliability can be realized than a MIS transistor having a normal structure.

[0025]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the structure of an n-channel MOSFET according to a first embodiment of the semiconductor device of the present invention, which has a structure having a constant energy layer.

In this figure, reference numeral 11 denotes a p-type silicon substrate, and an n-channel element portion is formed in a surface side region of the substrate 11. In other words, in the region near the surface of the substrate 11, n
⁺ Source region 12 and n ⁺ drain region 13 are formed on one main surface of substrate 11 and in source region 1.
A gate oxide film 14 is formed between the gate electrode 2 and the drain region 13, and a gate electrode 15 is formed on the gate oxide film 14.

Source region 1 of the element section on substrate 11
The semiconductor region except the 2 and the drain region 13 has a two-layer structure, of which the upper layer portion located immediately below the gate oxide film 14 is formed slightly deeper than the channel depth to be formed and is formed of single crystal silicon. A channel forming layer 16 is formed, and a lower layer portion located immediately below the channel forming layer 16 is made of an SiGe alloy synthesized with the same composition ratio of 75% Si and 25% Ge over the entire area of silicon and germanium. With respect to the hole energy, it is formed as a constant energy layer 17 lower than the channel forming layer 16 and in a constant energy state over the entire region.

Next, the operation of the present embodiment will be described with reference to FIG. FIG. 19A is a cross-sectional view of an n-channel MOSFET according to the present reference example, and FIG.
4 is a graph showing an energy state of holes in a cross section cut along a cutting line AA shown in FIG. In FIG. 19A, when an appropriate potential is applied to each of the gate electrode 15, the source region 12, and the drain region 13,
Electrons, which are main conduction carriers shown by black circles, travel in the p-type channel formation layer 16 from the n-type source region 12 to the n-type drain region 13 and cause impact ionization near the n-type drain region. On the other hand, as can be seen from FIG. 19B, the energy state of the constant energy layer 17 for holes is adjusted to a state lower than the energy state of the p-type channel formation layer 16. For this reason, holes generated by the ion collision (shown by white circles in FIG. 19A)
Move quickly so as to be drawn into the constant energy layer 17 having lower energy than the p-type channel formation layer 16, and are eventually absorbed by the n-type source layer 12.

As a result, holes hardly penetrate into the gate oxide film 14 and fluctuations in transistor characteristics are suppressed.
Therefore, higher reliability can be obtained than in the prior art.

Further, since the holes can be separated from the channel in the channel forming layer 16, the accumulation of holes near the channel can be prevented. In this respect, the variation in transistor characteristics can be suppressed. It is possible to realize higher reliability than the prior art.

Further, in this embodiment, the channel forming layer 16 containing no germanium is formed on the uppermost layer of the element layer. This has the effect of minimizing the generation of interface states at the interface with the gate oxide film 14. In addition, there is an effect that the forbidden band width in this portion where the channel current flows is kept large to prevent the collision ionization rate from increasing.

FIG. 2 shows a structure of an n-channel MOS transistor according to a second reference example of the present invention. In addition to the constant energy layer, a semiconductor is provided between the channel forming layer and the constant energy layer from the gate oxide film side. The structure has a transition layer whose energy decreases toward the substrate, that is, in the depth direction of the substrate.

In this figure, reference numeral 21 denotes a p-type silicon substrate, and an element portion is formed on the substrate 21.
22 is an n ⁺ type source region, 23 is an n ⁺ type drain region,
24 is a gate oxide film and 25 is a gate electrode.

The source region 2 of the element section on the substrate 21
The semiconductor region excluding the second and drain regions 23 has a three-layer structure, of which the upper layer portion located immediately below the gate oxide film 24 is formed slightly deeper than the channel depth to be formed and is formed of single crystal silicon. The intermediate layer located immediately below the channel forming layer 26 is made of a SiGe alloy, and the composition ratio of silicon and germanium (Si: Ge) is 100.
From 0% to 75%: 25%, the transition layer 27 linearly changes in the depth direction of the substrate 21, thereby forming a transition layer 27 in which the energy for holes gradually decreases continuously in the depth direction of the substrate 21. ing. In the lowermost layer immediately below the transition layer 27, silicon and germanium are formed over the entire area, and S
Si synthesized at the same composition ratio of 75% i and 25% Ge
It is formed as a constant energy layer 28 made of a Ge alloy.

Next, the operation of this embodiment having the above structure will be described with reference to FIG. FIG. 20A is a cross-sectional view of the n-channel MOSFET according to this reference example.
20B is a graph illustrating an energy state with respect to holes in a cross section taken along a cutting line AA illustrated in FIG. In FIG. 20A, when an appropriate potential is applied to each of the gate electrode 25, the source region 22, and the drain region 23, electrons that are main conduction carriers indicated by black circles are transferred from the n-type source region 22 to the n-type drain. It travels through the p-type channel formation layer 26 toward the region 23 and causes impact ionization near the n-type drain region. On the other hand, FIG.
As can be seen from (b), the constant energy layer 2 for holes
8 is adjusted to a state lower than the energy state of the p-type channel forming layer 26, and the energy state of the transition layer 27 is continuously changed from the energy state of the p-type channel forming layer 26 to the energy state of the constant energy layer 28. Has been adjusted to be lower. That is, a pseudo electric field that accelerates holes to a deeper portion of the substrate 21 is generated, so that holes generated by the ion bombardment (indicated by white circles in FIG. 20A) are removed from the p-type channel forming layer. It moves to the constant energy layer 28 having lower energy than 26 so as to be drawn at a higher speed than in the first reference example. Therefore, holes are separated from the gate oxide film 24 at a higher speed than in the first embodiment, so that higher reliability can be realized than in the first embodiment.

FIG. 3 shows the structure of an n-channel MOSFET according to a third embodiment of the present invention, which corresponds to the structure shown in FIG. 2 from which a channel forming layer is omitted. And a transition layer, and the transition layer also serves as a channel forming layer.

In this figure, reference numeral 31 denotes a p-type silicon substrate, and an element portion 32 is an n ⁺ -type source region of an element portion formed on the substrate 31; 33 is an n ⁺ -type drain region; A gate oxide film 35 is a gate electrode.

The source region 3 in the element portion on the substrate 31
The semiconductor region excluding the second and drain regions 33 has a two-layer structure, of which the upper layer located immediately below the gate oxide film 34 is formed sufficiently deeper than the channel depth to be formed and is made of a SiGe alloy. The composition ratio of silicon and germanium (Si: Ge) is 100%: 0.
% To 75%: a linear transition in the depth direction of the substrate 31 from 25% to 25%, thereby forming a transition layer 36 in which the energy for holes gradually decreases continuously in the depth direction of the substrate 31. In the lowermost layer immediately below the transition layer 36, silicon and germanium cover the entire area, and Si is 75%.
% And Ge are formed as a constant energy layer 37 made of a SiGe alloy synthesized at the same composition ratio of 25%.

The FET of this embodiment having such a structure
According to this, a similar electric field as described above is generated immediately below the gate oxide film 34, so that the holes move away from the gate oxide film 34 and the channel formation region more rapidly than in the second reference example shown in FIG. In addition, the light is discharged from the source region 32.

FIG. 4 shows the structure of the SOI n-channel MOSFET according to the first embodiment of the present invention. This structure is obtained by combining the SOI structure with the structure of the first embodiment shown in FIG. Equivalent to.

In this figure, reference numeral 41 denotes a p-type silicon substrate. On the substrate 41, an interlayer isolation oxide film 42 for electrically insulating and separating the substrate 41 from an element layer thereover and providing an SOI structure is provided. Is formed. 43 is the substrate 4
N ⁺ -type source region of the element portion formed on 1, also n ⁺ -type drain region 44, 45 is a gate oxide film, 46 is a gate electrode.

The source region 4 in the element portion on the substrate 41
The semiconductor region excluding the drain region 3 and the drain region 44 has a two-layer structure. Among them, the upper layer portion located immediately below the gate oxide film 45 is formed slightly deeper than the channel depth to be formed and is made of single crystal silicon. Forming layer 47
In a lower layer portion located immediately below the channel forming layer 47, silicon and germanium are formed over the entire area thereof.
S synthesized at the same composition ratio of 75% Si and 25% Ge
It is formed as a constant energy layer 48 made of an iGe alloy.

According to this embodiment, the impurity concentration of the channel forming layer 47 on the isolation oxide film 42 can be made lower than that of the MIS transistor having the normal structure without the SOI structure.
The holes generated by the impact ionization are easily diffused in a direction away from the channel forming region side, and higher reliability can be realized as compared with a MIS transistor having a normal structure.

FIG. 5 shows the structure of an SOI type n-channel MOSFET according to a second embodiment of the present invention, which is a combination of the SOI structure and the structure of the second embodiment shown in FIG. Equivalent to.

In this figure, reference numeral 51 denotes a p-type silicon substrate, on which an interlayer isolation oxide film 52 is formed, and 53 is an n ^{+ of} an element portion formed on the oxide film 52. A source region, 54 is an n ⁺ -type drain region, 55 is a gate oxide film, and 56 is a gate electrode.

The semiconductor region excluding the source region 53 and the drain region 54 in the element portion on the oxide film 52 has a three-layer structure, of which the uppermost layer located immediately below the gate oxide film 55 is a channel to be formed. The channel formation layer 57 is formed slightly deeper than the depth and made of single crystal silicon. The intermediate layer located immediately below the channel formation layer 57 is made of a SiGe alloy, and has a composition ratio of silicon and germanium (Si: Ge) is 100%: 0
% To 75%: a transition layer 57 that linearly changes in the depth direction of the substrate 51 from 25% to 25%, whereby the energy for holes gradually decreases continuously in the depth direction of the substrate 51. In a lower layer portion immediately below the transition layer 57, silicon and germanium cover the entire area, and Si
% And Ge are formed as a constant energy layer 58 made of a SiGe alloy synthesized at the same composition ratio of 25%.

According to the present embodiment, the presence of the transition layer 57 makes it easier for holes generated by impact ionization to leave the channel formation region than in the first embodiment shown in FIG.

FIG. 6 shows the structure of an SOI n-channel MOSFET according to a third embodiment of the present invention, which has a combination of the SOI structure and the structure of the third embodiment shown in FIG. Is equivalent to

In this figure, 61 is a p-type silicon substrate, 62 is an interlayer isolation oxide film on this substrate 61, 63 is an n ⁺ type source region of an element portion formed on this oxide film 62, and 64 is the same. An n ⁺ type drain region, 65 is a gate oxide film, and 66 is a gate electrode.

The semiconductor region excluding the source region 63 and the drain region 64 in the element portion on the oxide film 62 has a two-layer structure, of which the upper layer portion located immediately below the gate oxide film 65 has a channel depth to be formed. And is made of a SiGe alloy with a composition ratio of silicon and germanium (Si: Ge) of 100
From 0% to 75%: 25%, the transition layer 67 linearly changes in the depth direction of the substrate 61, thereby forming a transition layer 67 in which the energy for holes gradually decreases continuously in the depth direction of the substrate 61. ing. The lower layer immediately below the transition layer 67 is
SiGe synthesized with the same composition ratio of 75% Si and 25% Ge over the entire area of silicon and germanium
It is formed as a constant energy layer 68 made of an alloy.

Therefore, according to the present embodiment, holes generated by impact ionization are more easily separated from the channel forming region than in the second embodiment shown in FIG.

FIG. 7 shows the structure of an n-channel MOSFET according to a fourth embodiment of the present invention. The structure shown in FIG. 7 is obtained by removing the constant energy layer from the FET of the second embodiment shown in FIG. And has only a transition layer in the depth direction.

In this figure, 71 is a p-type silicon substrate, 72 is an n ⁺ -type source region of an element portion formed on the substrate 71, 73 is an n ⁺ -type drain region, 74 is a gate oxide film, and 75 is a gate oxide film. It is a gate electrode.

The source region 7 in the element portion on the substrate 71
The semiconductor region excluding the second and drain regions 73 has a three-layer structure including the base layer serving as the substrate 71, and the upper layer portion located immediately below the gate oxide film 74 is slightly smaller than the channel depth to be formed. The channel formation layer 76 is formed deeply and is made of single crystal silicon. The lower layer portion is made of a SiGe alloy, and the composition ratio of silicon and germanium (Si: Ge) is 100%: 0%.
From 75% to 25% in the depth direction of the substrate 71, and the transition layer 77 is formed in which the energy for holes gradually and continuously decreases in the depth direction of the substrate 61.

Also in this embodiment, the presence of the transition layer 77 immediately below the channel allows holes to be easily separated from the channel formation region, makes it difficult for holes to be accumulated in the SiGe layer, and suppresses the parasitic bipolar effect. can do.

FIG. 8 shows the structure of an n-channel MOSFET according to a fifth embodiment of the present invention. Here, the constant energy layer is removed from the FET of the third embodiment shown in FIG. 1 shows a structure having the above structure.

In this figure, 81 is a p-type silicon substrate, 82 is an n ⁺ -type source region of an element portion formed on the substrate 81, 83 is an n ⁺ -type drain region, 84 is a gate oxide film, and 85 is a gate oxide film. It is a gate electrode.

Source region 8 in the element section on substrate 81
The semiconductor region except the second and drain regions 83 has a two-layer structure including the base layer made of the substrate 81, and the upper layer portion located immediately below the gate oxide film 84 is formed deeper than the channel depth to be formed. And a SiGe alloy having a composition ratio of silicon and germanium (Si:
Ge) is 100%: 0% to 75%: 25%.
1, the energy of the transition layer 8 changes linearly in the depth direction, and the energy for holes gradually and continuously decreases in the depth direction of the substrate 81.
6 are formed.

Therefore, according to the present embodiment, further effects can be expected as compared with the fourth embodiment shown in FIG.

FIG. 9 shows the structure of an SOI type n-channel MOSFET according to a fourth embodiment of the present invention. The structure shown in FIG. 9 corresponds to a combination of the SOI structure and the structure shown in FIG. I do.

In this figure, reference numeral 91 denotes a p-type silicon substrate, 92 denotes an interlayer isolation oxide film formed on the substrate 91, and 93 denotes an n ^{+ of} an element portion formed on the oxide film 92.
Source region, 94 is also an n ⁺ type drain region, 95
Is a gate oxide film, and 96 is a gate electrode.

The semiconductor region excluding the source region 93 and the drain region 94 in the element portion on the oxide film 92 has a two-layer structure, and the upper layer portion located immediately below the gate oxide film 95 has a channel depth to be formed. The channel formation layer 97 is formed deeper than that and is made of single crystal silicon, and a layer below the channel formation layer 97 is made of a SiGe alloy, and the composition ratio of silicon and germanium (Si : Ge) is 100%: 0%
From 75% to 25% as a transition layer 98 that changes linearly in the depth direction of the substrate 91.

Therefore, according to the present embodiment, since it has an SOI structure, further effects are expected compared to the fourth reference example shown in FIG. 7, and the SOI floating effect can be suppressed.

FIG. 10 shows an SOI according to a fifth embodiment of the present invention.
It shows a structure of a type n-channel MOSFET, in which a structure having a combination of the SOI structure and the structure shown in FIG. 8 is shown.

In this figure, 101 is a p-type silicon substrate, 102 is an interlayer isolation oxide film formed on this substrate 101, 103 is an n ⁺ type source region of an element portion formed on this oxide film 102, 104 Denotes an n ⁺ type drain region, 105 denotes a gate oxide film, and 106 denotes a gate electrode.

The semiconductor region excluding the source region 103 and the drain region 104 in the element portion on the oxide film 102 is a transition layer 107 which also serves as a channel forming layer over the entire region. This transition layer 107 is also made of SiG
e alloy, and the composition ratio of silicon and germanium (Si: Ge) is 100%: 0% to 75%: 25%.
The substrate is formed so as to linearly change in the depth direction of the substrate 101.

Therefore, according to the present embodiment, it is possible to expect more effects than the fourth embodiment shown in FIG.

FIG. 11 shows an SOI according to a sixth embodiment of the present invention.
It shows the structure of an n-channel type MOSFET, and its feature is that, in addition to the charge having the polarity opposite to that of the main conduction carrier, in addition to the depth direction of the substrate, the direction from the drain region to the source region (hereinafter, referred to as For the sake of convenience, the transition in the horizontal direction is abbreviated).

In this figure, reference numeral 201 denotes a p-type silicon substrate, on which an interlayer isolation oxide film 202 for providing an SOI structure is formed, and an element isolation oxide film 203 surrounding an element formation region. Are formed.

Reference numeral 204 denotes an n ⁺ type source region of the element portion;
5 is an n ⁺ type drain region, 206 is a gate oxide film, 20
7, a gate electrode; 208, an interlayer isolation oxide film for electrically insulating and separating an element layer and a wiring layer; 209, a source electrode;
Reference numeral 10 denotes a drain electrode. The semiconductor region on the oxide film 202 except for the source region 204 and the drain region 205 of the element portion has a three-layer structure, of which the upper layer portion located immediately below the gate oxide film 206 is made of single crystal silicon and covers the channel. The channel formation layer 211 is formed as deep as possible. The lower layer of the channel forming layer 211 is made of a SiGe alloy, and has a composition ratio of silicon and germanium (Si: G
e) is formed as a transition layer 212 that increases linearly in the depth and lateral directions from 100%: 0% to 75%: 25%. For example, the composition ratio (Si: Ge) at a location along the line AA ′ in FIG. 11 corresponding to the depth direction is 10
From 0%: 0% to 80%: 20%, the composition ratio (S) of a portion along the line BB ′ in FIG.
i: Ge) varies from 95%: 5% to 85%: 15%. Therefore, in the transition layer 212, the oxide film 2
02, and closer to the source region 204, the energy state for holes is lower. Transition layer 21
The lower layer 2 is a base layer 213 and is made of the same single crystal silicon as the substrate 201.

According to the present embodiment, in the transition layer 212, the closer to the oxide film 202, and the more the source region 20
4, the energy state with respect to the holes becomes lower, so that the electrons, which are the main current components of the SOI-type n-channel MOSFET, generate excessive holes generated by impact ionization near the drain and quickly increase the proportion of germanium. On the other hand, in the element region, in the deep direction opposite to the gate oxide film 206 side, it also plays a role of leading to the source region 204 side. Thus, it can be pulled out from the source electrode.

In this embodiment, the channel forming layer 211 containing no germanium is formed as the uppermost layer of the SOI element layer. This has the effect of minimizing the generation of interface states at the interface with the gate oxide film 206. This has the effect that the forbidden band width in this part where the channel current flows is kept large and the collision ionization rate is prevented from increasing.

Here, the MOS described so far has been described.
The manufacturing method of the first reference example shown in FIG. 1, the first embodiment shown in FIG. 4, and the sixth embodiment shown in FIG. 11 will be described below with reference to the drawings.

FIG. 12 illustrates the manufacturing process for obtaining the FET structure of the first reference example shown in FIG.

First, a SiG film is formed on a p-type silicon substrate 301.
The e-alloy film 302 and the single crystal silicon film 303 are formed in this order by UHV / CVD (Ultra High Vacuum / Chemical V).
aporDeposition) or MBE (Molecular Beam Epitax)
y) (FIG. 12A). In forming the SiGe alloy film 302, the composition ratio of silicon and germanium (Si: Ge = 75%: 25%) is maintained constant over the entire region by controlling the supply of these material gases. And can be varied in the depth direction or the lateral direction.

Next, an oxide film 304 is formed by thermally oxidizing the single crystal silicon film 303, and a polycrystalline silicon film 305 is formed on the oxide film 304 by the above UHV / CVD or MB.
It is deposited by the E method (FIG. 12B).

Subsequently, the oxide film 3 is formed by a lithography technique.
The gate oxide film 306 and the gate electrode 307 are formed by patterning the substrate 04 and the polycrystalline silicon film 305 (FIG. 12C).

Then, from the single crystal silicon film 303 side, S
Arsenic is ion-implanted to a depth that allows the n ⁺ -type source region 308 to enter the iGe alloy film 302.
And n ⁺ type drain region 309 are formed and
The e-alloy film 310 is formed as the low energy layer 310 and the single crystal silicon film 303 is formed as the channel formation layer 311 (FIG. 12D).

According to the above manufacturing steps, the MOSFET structure of the first reference example shown in FIG. 1 is obtained. In PECVD or MBE, if the composition ratio of germanium is continuously changed, the second (FIG. 2), the third (FIG. 3), the fourth (FIG. 7), and the fifth (FIG. 8) reference examples can be used. The structure is obtained by the same manufacturing process.

Next, a manufacturing process for obtaining the SOI type n-channel MOSFET structure of the first embodiment shown in FIG. 4 will be described with reference to FIG.

First, LPCVD is performed on a silicon substrate 401.
After forming the oxide film 402 by (Low Pressure Chemical Vapor Deposition), the SiGe alloy film 403 and the single crystal silicon film 404 are formed by UHV / CVD or MBE.
(FIG. 13A).

Next, oxide film 405 is formed by PECVD.
Is formed, an n ⁺ -type polycrystalline silicon film 406 is formed (FIG. 13B).

Subsequently, the oxide film 4 is formed by a lithography technique.
05 and the polycrystalline silicon film 406 are patterned to form a gate oxide film 407 and a gate electrode 408 (FIG. 13C).

Then, from the single crystal silicon film 404 side, S
Arsenic is ion-implanted to a depth that allows the n ⁺ -type source region 409 to enter the iGe alloy film 403.
And an n ⁺ drain region 410, and at the same time, a SiGe alloy film 403 between the two regions 409 and 410 is formed as a low energy layer 411 and a single crystal silicon film 404 is formed as a channel formation layer 412 (FIG. 13).
(D)).

According to the above manufacturing steps, the FET structure of the first embodiment shown in FIG. 4 is obtained. In addition, PECVD or M
In BE, if the composition ratio of germanium is continuously changed, the second (FIG. 5), the third (FIG. 6), the fourth (FIG. 9),
The structure of the fifth (FIG. 10) embodiment can be obtained by the same manufacturing process.

FIG. 14 illustrates the manufacturing process of the SOI type n-channel MOSFET shown in FIG.

First, a silicon oxide film 502 is formed with a thickness of about 1 μm on the entire surface of a semiconductor substrate 501 by a sputtering method, a CVD method or the like, and then a polycrystalline silicon film is formed on the silicon oxide film 502 by, for example, 6000 Å. Formed with thickness. Then, the polycrystalline silicon film is monocrystallized by using an electron beam annealing method, or an annealing method using a heater, and oxidized in an oxidizing atmosphere to remove the oxide film with a solution such as ammonium fluoride.
Alternatively, a single-crystal silicon film 503 having a thickness of about 1000 Å is formed by an etch-back method using dry etching such as RIE (FIG. 14A).

Next, a silicon-germanium alloy film 504 having a thickness of about 1000 angstroms is formed on the single crystal silicon film 503 by a high vacuum CVD method or a molecular beam epitaxial method. At this time, the supply of the source gas is controlled so that the ratio of germanium gradually decreases from the lower layer to the upper layer due to the above-described composition change. Thereafter, a mask or the like is applied to a portion to be on the drain side with a resist or the like.
After Ge ions are implanted by ev to remove the resist, annealing is performed, for example, at 600 ° C. for 24 hours, so that the Ge content can be distributed in the lateral direction. further,
Continuously single-crystal silicon film 50 containing no germanium
5 is formed on the SiGe alloy film 504, for example, on the order of 100 angstroms (FIG. 14B). Here, it is desirable that the single crystal silicon film 505 is doped with p-type impurities at a low concentration of 10 ¹⁶ cm ⁻³ or less.

After that, an oxide film is formed on the single crystal silicon
Angstrom is formed, and LPC is formed on this oxide film.
A polycrystalline silicon film serving as a gate electrode is formed at, for example, 4000 angstroms by a VD method or the like, and the oxide film and the polycrystalline silicon film are simultaneously patterned to form a gate oxide film 511 and a gate electrode 512. next,
Self-aligned on both sides of these gates, for example 10 ²⁰ cm
An n-type impurity such as arsenic having a high concentration of about ^-3 is ion-implanted and diffused to form a source region 507 of an n-channel transistor.
At the same time as forming the n-type diffusion layer to be the drain region 508, the single crystal silicon film 503 in the region other than these regions 507 and 508 is used as the base layer 506, the SiGe alloy film 504 is used as the transition layer 509, and the single crystal silicon film 505 is used as the single crystal silicon film 505. Each is formed as a channel forming layer 510 (FIG. 14
(C)).

Thereafter, a hole for a trench is opened, and in this state, a silicon oxide film is formed on the entire surface by a CVD method or the like. Then, contact holes reaching the source / drain regions 507 and 508 are opened. A source electrode 515 and a drain electrode 516 are formed as an isolation oxide film 514 and an interlayer isolation oxide film 513, and a metal wiring is buried in the contact hole. The device is formed (FIG. 14D). In this case, any material can be used for the electrodes 515 and 516 as long as they can make ohmic contact with the n-type diffusion layer.

In this embodiment, first, in order to form a single-crystal silicon film 503 to be the base layer 506 on the SOI oxide film 502, a polycrystalline silicon film is deposited first, and this is annealed to form a single-crystal silicon film. However, for example, a SIMOX method for forming a buried oxide film by ion implantation of oxygen atoms into a silicon substrate may be used. Alternatively, epitaxial growth may be performed directly on the insulating film.

Although a polycrystalline silicon film is used for the gate electrode 512, if a desired threshold can be obtained,
Other semiconductor materials, silicide compounds, and metals such as aluminum and tungsten may be used.

Further, in the above embodiment, as a means for changing the forbidden band in the transition layer 509, a SiGe alloy is used. In a SiGe alloy, when the germanium content is reduced to about 20%, the forbidden band becomes 0.1% less than that of silicon.
It becomes narrower than eV. In the case of the SiGe alloy, the change in the forbidden band is mainly due to the change in the valence band, and the electrons flowing in the conduction band are hardly affected. Due to the tilt of the valence band caused by the change, a force is applied toward the higher proportion of germanium. If the difference between the forbidden bands of 0.1 eV is 1000 angstroms, the electric field strength becomes 10 kV / cm, and holes can be caused to flow by this electric field. Therefore, n-channel SOIMO
An electron, which is a main current component of the SFET, plays a role of quickly flowing out excess holes generated by impact ionization near the drain in a direction in which the proportion of germanium is high, that is, in a deep direction opposite to the gate. Other than the SiGe alloy, any material can be used as long as it can smoothly reduce the forbidden band and the main part of the change is a change in the valence band.

Further, since the intrinsic carrier concentration is high where the forbidden band is narrow, the recombination probability of the holes that have flowed in increases. Also, in the case of remaining, the distance from the gate is longer than that of the conventional structure.
The drain current can be stabilized without changing the potential of the substrate as in T.

Further, in a p-channel SOI MOSFET, if a substance whose forbidden band can be smoothly reduced and a main part of the change is a change in the conduction band is used, the above-described SOI n-channel MOSFET can be used. A high-performance SOI p-channel MOSFET similar to that described above is possible.

[0097]

As is apparent from the above description, according to the present invention, the substrate side has lower energy for the charge of the opposite polarity to the main conduction carrier than the surface portion of the channel formation layer, and the vicinity of the drain region The new charges generated by impact ionization move to the substrate faster than the conventional MIS transistor, so that high-energy charges are less likely to be injected into the gate insulating film, and the deterioration of the gate insulating film quality is suppressed. Will be done.

Further, since the new charges are less likely to be accumulated under the channel forming region, stable current-voltage characteristics can be obtained up to a high drain voltage.

Further, if a transition layer whose energy decreases from the gate insulating film side to the semiconductor substrate side is provided, charges generated by impact ionization can be quickly discharged to the lower part.

Particularly, in the SOI type MIS transistor, the impurity concentration of the channel forming layer on the isolation oxide film can be made lower than that of the MIS transistor having the normal structure without the SOI structure. Electrons or holes easily diffuse in a direction away from the gate insulating film. Therefore, higher reliability can be realized than a MIS transistor having a normal structure.

[Brief description of the drawings]

FIG. 1 shows an n-channel MOSF according to a first reference example of the present invention.
FIG. 4 is a cross-sectional view of the element showing the structure of the ET.

FIG. 2 shows an n-channel MOSF according to a second reference example of the present invention;
FIG. 4 is a cross-sectional view of the element showing the structure of the ET.

FIG. 3 shows an n-channel MOSF according to a third embodiment of the present invention;
FIG. 4 is a cross-sectional view of the element showing the structure of the ET.

FIG. 4 is an element sectional view showing the structure of an SOI n-channel MOSFET according to the first embodiment of the present invention.

FIG. 5 is an element sectional view showing the structure of an SOI n-channel MOSFET according to a second embodiment of the present invention.

FIG. 6 is an element sectional view showing the structure of an SOI n-channel MOSFET according to a third embodiment of the present invention.

FIG. 7 shows an n-channel MOSF according to a fourth reference example of the present invention.
FIG. 4 is a cross-sectional view of the element showing the structure of the ET.

FIG. 8 shows an n-channel MOSF according to a fifth embodiment of the present invention.
FIG. 4 is a cross-sectional view of the element showing the structure of the ET.

FIG. 9 is an element sectional view showing the structure of an SOI n-channel MOSFET according to a fourth embodiment of the present invention.

FIG. 10 is an element sectional view showing the structure of an SOI n-channel MOSFET according to a fifth embodiment of the present invention.

FIG. 11 shows an n-channel MOS according to a sixth embodiment of the present invention.
FIG. 3 is an element cross-sectional view illustrating a structure of an FET.

FIG. 12 is an element cross-sectional view showing a manufacturing process of the FET structure shown in FIG. 1 according to a step;

FIG. 13 is a sectional view of an element in a step showing a manufacturing process of the FET structure shown in FIG. 4;

FIG. 14 is a sectional view of an element showing a manufacturing process of the FET structure shown in FIG. 11;

FIG. 15 is an element cross-sectional view showing the structure of a conventional n-channel MOSFET.

FIG. 16 is an element sectional view showing a structure of a conventional SOI n-channel MOSFET.

FIG. 17 is an equipotential diagram showing a potential distribution in a conventional SOI type n-channel MOSFET.

18 is an SOI type n-channel MOSFE shown in FIG.
FIG. 4 is a curve diagram showing VD-ID characteristics at T.

FIG. 19 is a view for explaining the operation of the first reference example.

FIG. 20 is a view for explaining the operation of the second reference example;

[Explanation of symbols]

11, 21, 31, 41, 51, 61, 71, 81, 9
1,101,201 p-type silicon substrate 12,22,32,43,53,63,72,82,9
3,103,204 n ⁺ type source regions 13,23,33,44,54,64,73,83,9
4,104,205 n ⁺ type drain regions 14,24,34,45,55,65,74,84,9
5,105,206 Gate oxide film 15,25,35,46,56,66,75,85,9
6, 106, 207 Gate electrode 16, 26, 47, 57, 76, 97, 211 Channel forming layer 17, 28, 37, 48, 59, 68 Constant energy layer 27, 36, 58, 67, 77, 86, 98 , 107,
212 transition layer 42,52,62,92,102,202 interlayer isolation oxide film

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-1-120067 (JP, A) JP-A-61-4280 (JP, A) JP-A-3-3366 (JP, A) JP-A-63-1988 252478 (JP, A) JP-A-63-313865 (JP, A) JP-A-2-100327 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 29/78

Claims (6)

(57) [Claims] A semiconductor substrate; an insulating separation layer formed on the semiconductor substrate; a SiGe layer formed on the insulating separation layer; and a first conductivity type silicon region formed on the SiGe layer. A source region and a drain region of a second conductivity type formed apart from each other in the silicon region; a channel region provided on the surface of the silicon region between the source region and the drain region; A semiconductor device, comprising: a gate insulating film formed thereon; and a gate electrode formed on the gate insulating film. 2. The SiGe layer according to claim 1, wherein said SiGe layer is in a state of energy in which a carrier having a charge having a polarity opposite to that of a main conduction carrier conducting said channel region is attracted. Semiconductor device. 3. The semiconductor device according to claim 1, wherein said SiGe layer includes a first layer in which a composition ratio of Si and Ge is substantially constant. 4. The SiGe layer according to claim 1, wherein the SiGe layer includes a second layer in which the concentration of Ge increases from zero as the distance from the interface with the silicon region increases. Semiconductor device. 5. The semiconductor device according to claim 3, wherein the first layer is a constant energy layer having a constant energy state over the entire area. 6. The semiconductor device according to claim 4, wherein said second layer is a transition layer in an energy state in which said carriers are accelerated.