JPS626254B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a large-scale integrated circuit (hereinafter referred to as an LSI circuit), in particular, which has one or more registers connected to a data bus, and which has one or more registers connected to a data bus. Concerning LSI circuits that require individual bit control.

Central processing unit of electronic computer or electronic exchange (hereinafter referred to as
CPU (denoted as CPU) has registers that display various statuses. This type of register is usually connected to a data bus because it needs to be followed by software (programs). on the other hand,
It is necessary to individually change (set or reset) the status of the status register in response to an external request such as when the CPU changes from a run state to a stop state. Further, there also arises a need to output one of the bits of the status register to the outside during normal operation and display it on a console panel.

Traditionally, multiple registers containing this type of register were used.
In LSI chips, when the status registers and bit positions that need to be controlled individually differ from chip to chip, the number of chip types increases because the bits of each necessary status register are individually connected to external terminals. There were increasing drawbacks.
Furthermore, in order to solve this drawback, it is not a good idea to connect all the bits of all the status registers to external terminals individually, as this would increase the number of terminals.

The present invention has been made in view of the above-mentioned conventional circumstances, and an object of the present invention is to have a terminal that selects and individually controls arbitrary bits of arbitrary status registers according to instructions from outside the LSI. Therefore, it is an object of the present invention to provide a new LSI circuit which solves the above-mentioned drawbacks and allows the number of types of LSI chips to be reduced.

That is, according to the present invention, in an LSI configuration having one or more registers connected to a data bus, the terminal independent from the data bus and the
The LSI has a distribution circuit that selects any bit of any register among the registers according to an instruction from outside the LSI and forms a line separate from the data bus that connects the selected bit to the terminal. , is characterized in that any bit of any register is individually controlled via the above terminal and the above line.
An LSI circuit is given.

Next, preferred embodiments of the present invention will be specifically explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In one embodiment of the present invention, in the LSI chip 1,
n status registers 31 to 3n connected to the outside via data bus 2; distribution circuits 41 to 4n and 5 for selecting status registers and status register bits connected to terminal 6; and selection of these distribution circuits. It consists of a register 7 that holds signals. The distribution circuits 41 to 4n, 5 can be easily constructed by, for example, D-multiplexers. In this embodiment, the 0 bit of status register 3n can be set or reset by a signal from terminal 6 independently of data bus 2. In the figure, this state is indicated by a thick line. First, by writing the register number n and bit position (0) to be individually set or reset to the selection signal holding register 7 via the data bus 2, the terminal 6 and any one bit of any register are set. Can be connected. As long as the selection signal is held in register 7, data bus 2
status register 3n from terminal 6 regardless of
can be controlled (set or reset).

FIG. 2 is a block diagram showing another embodiment of the invention. The difference from the embodiment shown in FIG. 1 is that the register and bit selection signal are outputted to the outside of the LSI chip 1 through a terminal 8 instead of the selection signal holding register 7. In this embodiment, register and bit selection is performed by applying a fixed level to terminal 8.

In the above embodiment, terminal 6 was an input terminal, but
Replace the distribution circuits 41 to 4n and 5 with selection circuits,
By using the terminal 6 as an output terminal, the selection bit can be constantly output to the outside. Further, in the above example, only one terminal 6 is provided, but by providing a plurality of selection signal holding registers 7 and distribution circuits 5, a plurality of terminals 6 can be provided.

As explained above, the present invention provides an input terminal that can individually set and reset any bit of any status register by selecting any bit in accordance with an instruction from outside the LSI, or an output terminal that can individually output a constant output. This not only reduces the number of pins compared to fixedly outputting some bits of the status register to the LSI pins, but also
The effect is also significant from the perspective of increasing repeatability.

Although the present invention has been described above with respect to its preferred embodiments, these are merely illustrative, and it goes without saying that the present invention is not limited only to the embodiments described herein.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the LSI circuit according to the present invention, and FIG. 2 is a block diagram showing another embodiment of the LSI circuit according to the present invention. 1...LSI, 2...Data bus, 31~3n...
...n status registers, 41 to 4n...n
5...Distribution circuit (bit selection), 6...Terminals connected to individually selected bits, 7...Status register and bit selection signal holding register, 8...Status Register and bit selection signal input terminal.

Claims (1)

[Claims] 1. In a large-scale integrated circuit configuration having one or more registers connected to a data bus, a terminal independent from the data bus and an instruction from outside the large-scale integrated circuit can be used to control any register among the registers. and a distribution circuit forming a line separate from the data bus that selects the selected bit and connects the selected bit to the terminal, and connects the selected bit to the terminal via the terminal and the line. A large-scale integrated circuit characterized by the ability to control bits individually.