JPH04346140A - Access controller for shared memory - Google Patents

Abstract

PURPOSE:To realize simple hardware configuration by giving an equipment requiring high speed processing a high priority order and enabling access without deteriorating the frequency of access even in an equipment with low priority order. CONSTITUTION:The controller is segmented into an equipment (master 1) with fixed high priority order and an equipment (master 2) with low priority following the rotation priority order by the rotation priority order circuit. The rotation priority order circuit is provided with a next priority order decision circuit 11 deciding the equipment having the next priority order in the former priority order and port selection circuits 131, 132, and 133 receiving the access demand of the equipment according to the next priority order of the next priority order decision circuit 11 when there is an access demand from more than one equipment following the rotation priority order and receiving the access demand of an equipment having the further next priority order when there is no access demand from the equipment corresponding to the next priority order.

Description

[Detailed description of the invention]

0001

[Field of Industrial Application] The present invention relates to a shared memory access control device used when a plurality of processors etc. directly access a shared memory, and in particular, the present invention relates to a shared memory access control device that is used when a plurality of processors etc. directly access a shared memory. The present invention relates to an access control device.

0002

[Prior Art] Conventionally, regarding the priority order of shared memory when multiple processors directly access shared memory,
There are fixed priority methods and rotating priority methods.

[0003] The former fixed priority system is a system in which the priorities among the processors are fixedly determined in advance, as shown in FIG. 4(a). Incidentally, in the example of FIG. 4A, ch0 has the highest priority among the four processors ch0 to ch3, and the priorities descend in the order of ch1, ch2, and ch3. That is, once an access request for one channel is accepted, access requests for other channels are not accepted until the process for that channel is completed.

On the other hand, the latter rotation priority system is shown in FIG.
As shown in b), the priority order is rotated every time an access request for a certain channel is processed, the first channel processed becomes the lowest order, and the priority orders of other channels change accordingly. In the example of FIG. 4(b), in the initial state, among the four processors ch0 to ch3, c
h0 has the highest priority, ch1, ch2, ch
The priority order decreases in order of 3. Now, if an access request for channel ch2 is processed, the priority changes to ch3, ch0, ch1, and ch2. next,
When an access request for channel ch0 is processed, the priority changes to ch1, ch2, ch3, ch0, and when an access request for channel ch1 is processed, the priority changes to ch2, ch3, ch0, ch1.

[0005]

[Problem to be Solved by the Invention] However, the above-mentioned fixed priority system and rotating priority system have
Each has the following problems. First, in the fixed priority system, when access requests to the shared memory are generated simultaneously from multiple processors, the processor with the higher priority always performs the access processing, and the access frequency of the processor with the lower priority decreases significantly.

On the other hand, in the rotating priority system, the frequency of access to the shared memory is averaged for each processor, so even if some processors require high-speed processing, once the shared memory is accessed, the priority Since the ranking is the lowest, there is a problem that the processing speed cannot be increased.

[0007] In this way, in conventional shared memory priority determination, when high-priority processors and low-priority processors coexist, the access frequency of the low-priority processor decreases, or high-speed processing is delayed. There is a problem in that the processing speed cannot be increased if the required processor is used.

The present invention was made in view of the above-mentioned circumstances, and even if there are devices with high priority and devices with low priority, high priority is given to devices that require high-speed processing. The present invention aims to provide a shared memory access control device that achieves good responsiveness, allows access frequency to a certain level even for devices with low priority, and is realized with a simple hardware configuration.

[0009]

[Means for Solving the Problems] In order to solve the above problems, the present invention provides a shared memory access control device when a plurality of devices commonly and selectively access the shared memory.

[0010]According to the present invention, the access request from each device is processed by pre-distributing devices into a fixed group of high priority groups and devices with low priority according to the rotation priority order by a rotation priority circuit; The rotation priority order circuit includes a next priority order determination circuit that determines the next priority device based on the previous priority order, and a next priority order determination circuit that determines the next priority device based on the previous priority order, and a Selecting a port that accepts an access request from a device according to the next priority of the ranking determining circuit, and also accepts an access request from a device with the next priority according to the rotating priority when there is no access request from a device corresponding to the next priority. The configuration includes a circuit.

[0011]

[Operation] Therefore, by taking the above-mentioned measures, the present invention can perform access processing at an appropriate processing speed by assigning devices that require high-speed processing to groups with high priority. In the case of a device with a low rotational priority, the rotational priority is followed, but if an access request arrives from a device other than the device with the next priority according to the rotational priority, unless an access request arrives from a device with the next priority. , it is possible to perform access processing by giving priority to devices other than those listed above, so that even devices with low priority can perform access processing without reducing access frequency.

0012

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a schematic configuration of a shared memory access control device according to the present invention. Note that master 1 (port 0) and master 2 (port 1) are
, port 2, and port 3), and four devices (for example, processors) access the shared memory in common.

In other words, this device has four ports: master 1 (port 0) and master 2 (port 1, port 2, port 3).
A signal REQ, that is, an access request RE to the shared memory, is sent to the other device via an interface (not shown).
It is comprised of a priority order determination circuit 10 that receives Q and determines the priority order and returns a signal ACK representing the determination result to the device, a timing control means 21, and a shared memory 22.

[0014] This priority order determination circuit 11 has access requests REQ to the shared memory 22 for different groups, that is, port 0 and port 1 of master 1 and master 2,
2 and 3 at the same time, the access request REQ from the device (port 0) of a predetermined high priority group (for example, master 1) will be accepted with priority and access processing will be performed, and the shared memory When access requests REQ for 13 are generated simultaneously from devices (ports 1, 2, and 3) in the same group (master 2 in this case), rotating priority is used to rotate the priority every time the access request REQ for each device is processed. Shared memory 22 according to the ranking method
It has the ability to access.

The timing control means 21 controls the clock signal CL according to the access from the priority determination circuit 11.
It has a function to perform necessary control on the shared memory 22 based on K, such as read, write, and other controls.

Next, FIG. 2 is a diagram showing a specific configuration of the priority order determining circuit 10. As shown in FIG. In the same figure, reference numeral 11 is a next priority determining circuit which has the role of an encoder, and when it receives the access control signal Y1, Y2, Y3 related to one port in the same group (master 2), it determines the previous priority order. The select signal generation circuit 12 determines the port with the next priority based on the ranking and generates the ranking determination signal S1 consisting of 2 bits.
Send to. This select signal generation circuit 12 uses, for example, a register, and outputs a port select signal S2, which also consists of 2 bits, from the ranking determination signal S1.

131, 132, 133 are sect signals S2 consisting of 2 bits in response to access requests REQ from each port 1, 2, 3 of the same group (master 2).
a port selection circuit that judges the contents of and accepts an access request REQ for one port; 140, 141, 142;
, 143 are latch circuits composed of inhibit circuits and other logic circuits, and these latch circuits 14
0 to 143 are access requests R from port 0 of master 1, port selection circuits 131, 132, 133, etc.
EQ (S3) is held by strobe signal Ss.

151, 152, 153 are latch circuits 1 corresponding to each port in the same group (master 2)
Same group port selection which accepts the latch data held in 41, 142, 143 based on the contents of the 2-bit port selection signal S4 from the port selection circuits 131, 132, 133 and outputs a signal of "1". It is a circuit. 160 , 161 , 162
, 163 are connected to each circuit 140 or 151 , 152 , when the gate signal Sg of "1" is input.
This is a gate circuit that takes in a "1" signal from 153 and outputs an access control signal Y0 or Y1, Y2, Y3.

Note that the gate circuits 160, 161, 1
Access control signal Y output from 62, 163
0 or Y1, Y2, Y3 are sent to the next priority determination circuit 11 which determines the next priority, and the access control signal Y
0 or Y1, Y2, and Y3 are sent to the timing control means 21, each master 1, 2, or a common device of each master 1, 2, etc. through corresponding latch circuits (not shown), and which port is accessed. It is also used as a signal to block a strobe signal corresponding to master 1, which has a high priority, when accessing a certain port.

Next, the operation of the apparatus configured as above will be explained. First, port 0 of master 1 or master 2
When accessing ports 1, 2, and 3, these masters 1, 2
Alternatively, a gate signal 11g for opening the gate is introduced from a common device of each master 1, 2 to each gate circuit 160-163. In this state, the initial value priority of each port is port 0, port 1, port 2,
The order is port 3, but port 0 of master 1 has a fixed priority, and ports 1 and 2 of master 2 have fixed priority.
, 3, rotation is given priority.

Therefore, when access requests REQ are generated simultaneously from devices (port 0 and ports 1, 2, and 3) of different groups (master 1 and master 2), the access request REQ of port 0 is first sent to the latch circuit 140. After being latched by the latch circuit 140, the gate circuit 1
61, the access control signal Y0 is output.

On the other hand, an access request REQ from a certain port of the master 2 is received by each port selection circuit 131 , 132 ,
133, respectively, are input to different terminals. At this time, the next priority order determination circuit 11 sends a rank determination signal S1 and a select signal S2 corresponding to the next priority according to the rotation order to each port selection circuit 131, 132, 13.
It comes in at 3. Here, these port selection circuits 13
1, 132, and 133 determine the next priority, but when the access request REQ is not coming from the port corresponding to the next priority, if the access request REQ is coming from the next port according to the rotation order. is a port selection circuit 131 or 132 corresponding to the relevant port.
, 133 to access request S3 and port selection signal S
Outputs 4. Therefore, after the fixed priority host 0 accesses the shared memory 21, the port after the order change accesses the shared memory 22.

On the other hand, the device (of the same group (master 2)
Similarly, when there is an access request REQ from ports 1, 2, 3), the port selection circuits 131, 132, 133 accept the access request REQ of the next priority port according to the next priority order determining circuit 11, and latch it in the latch circuit. At the same time, an access control signal is output from the gate circuit through the same group port selection circuit. At this time, for example, the access control signal Y2 is sent from the gate circuit 162.
When the access control signal Y2 is input to the corresponding terminal of the next priority order determining circuit 11, the order determining signal S1 for port 3, which is the next priority, is output according to the rotation order shown in FIG. .

Therefore, according to the configuration of the embodiment as described above, when access requests are issued to the shared memory 22 from devices in different groups at the same time, access requests are made to the shared memory 22 from devices of a fixedly determined high priority group. Device access request RE
When access processing is performed with priority given to Q, and access requests REQ are generated simultaneously from devices in the same group,
Each time an access request REQ is processed, access processing is performed according to the rotating priority system, so that even devices with low priority can be accessed without reducing access frequency.

Furthermore, when an access request REQ is received from a certain device in the same group, the port selection circuits 131 , 132 , 133
After confirming that there is no access request REQ for the next priority port, the access request REQ for the next priority port is further accepted and processed, so that a sufficient access frequency can be ensured. Furthermore, in the case of devices that require high-speed processing, responsiveness can be sufficiently improved by giving them a high priority in advance. Furthermore, the priority determination circuit 1
0 can be easily realized using logic circuits.

In the above embodiment, each port 0 to 3 is assumed to be a processor, but the device for each port 0 to 3 is not particularly limited. In addition, although one device has a fixed high priority and three devices belong to the same group, the number is not limited to these. In addition, the present invention can be implemented with various modifications without departing from the gist thereof.

[0027]

[Effects of the Invention] As explained above, according to the present invention, even if high priority devices and low priority devices coexist, high priority is given to devices that require high-speed processing. Therefore, it is possible to provide a shared memory access control device that has good responsiveness, allows access frequency to a certain level even for devices with low priority, and can be realized with a simple hardware configuration.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing an embodiment of a shared memory access control device according to the present invention.

FIG. 2 is a specific configuration diagram of the priority determination circuit 10 shown in FIG. 1.

FIG. 3 is a diagram showing changes in shared memory rotation priority.

FIG. 4 is a diagram illustrating the priority order of conventional shared memory.

[Explanation of symbols]

10... Priority order determination circuit, 11... Next priority order determination circuit,
12...Select signal generation circuit, 131, 132, 1
33...Port selection circuit, 140, 141, 142
, 143 ... latch circuit, 151 , 152 , 15
3...Same group port selection circuit, 160, 161
, 162, 163...Gate circuit, 22...Shared memory.

Claims (1)

[Claims] Claim 1: A shared memory access control device when a plurality of devices commonly and selectively access the shared memory, in which devices of a fixed high priority group are set in advance and rotation priority is given by a rotation priority circuit. The configuration is such that access requests from each device are processed by sorting them into devices with low priority according to the order, and the rotating priority circuit determines the device with the next priority based on the previous priority. a next priority order determining circuit and one according to the rotational priority order;
When there is an access request from more than one device, the access request of the device is accepted according to the next priority of the next priority determining circuit, and when there is no access request from the device corresponding to the next priority, the rotation priority is 1. A shared memory access control device, comprising: a port selection circuit that accepts an access request from a device with the next highest priority.