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JPS6259461B2 - - Google Patents

Info

Publication number
JPS6259461B2
JPS6259461B2 JP56006673A JP667381A JPS6259461B2 JP S6259461 B2 JPS6259461 B2 JP S6259461B2 JP 56006673 A JP56006673 A JP 56006673A JP 667381 A JP667381 A JP 667381A JP S6259461 B2 JPS6259461 B2 JP S6259461B2
Authority
JP
Japan
Prior art keywords
lead
leads
integrated circuit
substrate
hybrid integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP56006673A
Other languages
Japanese (ja)
Other versions
JPS57121266A (en
Inventor
Haruo Yamanaka
Kyoshi Goto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Priority to JP56006673A priority Critical patent/JPS57121266A/en
Publication of JPS57121266A publication Critical patent/JPS57121266A/en
Publication of JPS6259461B2 publication Critical patent/JPS6259461B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H10W90/00
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/03Use of materials for the substrate
    • H05K1/0306Inorganic insulating substrates, e.g. ceramic, glass
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/328Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by welding
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3405Edge mounted components, e.g. terminals

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【発明の詳細な説明】 本発明は混成集積回路の製造方法に関する。[Detailed description of the invention] The present invention relates to a method of manufacturing a hybrid integrated circuit.

従来、混成集積回路は第1図および第2図に示
すように製造している。すなわち、絶縁基板、た
とえばセラミツク基板1の一面に厚膜ペースト印
刷により形成された回路配線基板などの所要個所
に半田ペーストを印刷した後、この半田ペースト
上に集積回路素子(IC)、トランジスタ、ダイオ
ードなどの半導体素子2やコンデンサなどの部品
をマウントし、熱板などにより加熱、半田付け4
するとともに洗浄、フアンクシヨントリミング、
特性チエツクなどの工程を経てケース付け(図示
せず)する混成集積回路のアウタリードの取出方
法は次のように行つている。まず第1図Aのよう
にヘツド6を有するアウタリード5を基板1のア
ウタリード取出電極部に垂直に設置し、その電極
部で半田付けするものである。しかしこの方法で
は、リード5を1本づつ半田付けしなければなら
ず、よつて作業時間がかかり、量産的でない上、
基板1とリード5との接続が半田のみによるた
め、引張りに対して接着強度が弱いという欠点が
ある。
Conventionally, hybrid integrated circuits have been manufactured as shown in FIGS. 1 and 2. That is, after printing solder paste at required locations on an insulating substrate, such as a circuit wiring board formed by thick film paste printing on one side of a ceramic substrate 1, integrated circuit elements (ICs), transistors, and diodes are printed on the solder paste. Mount semiconductor elements 2 such as capacitors, etc., heat them with a hot plate, etc., and solder them 4.
Along with cleaning, function trimming,
The method for taking out the outer leads of a hybrid integrated circuit, which is attached to a case (not shown) after undergoing processes such as characteristic checking, is as follows. First, as shown in FIG. 1A, an outer lead 5 having a head 6 is installed perpendicularly to an outer lead extraction electrode portion of a substrate 1, and soldered to the electrode portion. However, with this method, the leads 5 must be soldered one by one, which takes time and is not suitable for mass production.
Since the substrate 1 and the leads 5 are connected only by solder, there is a drawback that the adhesive strength against tension is weak.

この接着強度を改良したものとして第1図Bに
示す方法がある。これは、基板1のアウタリード
5の植設部に穴孔7を設け、ヘツド16を有する
リード5を基板1の裏側から挿入するものであ
る。しかしこの方法では、リード5を裏側から1
本づつ挿入するため、作業性が悪い上、基板1の
表面でのハンダ付部分4の接触面積が少ないた
め、オープンになりやすい欠点がある。そこで、
この接触面積を大きくするよう改良したものとし
て第1図Cに示す方法がある。これは、アウタリ
ード5の中間に鍔8を有するものを用い、このリ
ード5を基板1の表面から挿入し、裏側に突出し
たリード5の部分をつぶすことにより強固に固定
するものである。しかしこの方法も、リード5を
1本づつ挿入しなければならず、しかも基板1の
裏側において、リード5の突出部分をつぶすとい
う作業工程が新たに増えるという欠点がある。
There is a method shown in FIG. 1B that improves this adhesive strength. In this case, a hole 7 is provided in the part of the substrate 1 where the outer lead 5 is installed, and the lead 5 having a head 16 is inserted from the back side of the substrate 1. However, with this method, lead 5 is
Since the soldering part 4 is inserted one by one, the workability is poor, and since the contact area of the soldered part 4 on the surface of the board 1 is small, there is a drawback that it tends to become open. Therefore,
There is a method shown in FIG. 1C that has been improved to increase this contact area. This uses an outer lead 5 having a flange 8 in the middle, inserts this lead 5 from the surface of the substrate 1, and firmly fixes it by crushing the portion of the lead 5 that protrudes to the back side. However, this method also has the disadvantage that the leads 5 must be inserted one by one, and furthermore, the work step of crushing the protruding portions of the leads 5 on the back side of the substrate 1 is added.

そこで、上述したようなリード5を1本づつ電
極部に半田付けするという煩雑さを解消したも
の、また引張りに対する接着強度を向上させたも
の、さらに基板1からの浮きを改良したものとし
て第2図に示すような方法がある。すなわち、第
2図A,Bは基板1にあらかじめ半田ペーストを
印刷しておき、この半田ペースト部に電子部品と
同時にリード5を半田付けするもので、複数のリ
ードが一体化されたリードフレームを用いるもの
である。また第2図Cは、第1図B,Cと同様に
基板1にあらかじめ穴孔7を設け、この穴孔7に
先端「ト」字状のリード5の突出部9を挿入し、
半田付けするものである。さらに第2図D,E
は、先端が凹状になつたリード5を用い、このリ
ード5の凹部10で基板1の電極部を喰わえ込む
ように設置し、この状態で半田付けして固定する
ものである。
Therefore, we have developed a second method that eliminates the complexity of soldering the leads 5 one by one to the electrode parts as described above, improves the adhesive strength against tension, and improves the floating from the substrate 1. There is a method as shown in the figure. In other words, in FIGS. 2A and 2B, solder paste is printed on the board 1 in advance, and the leads 5 are soldered to the solder paste part at the same time as the electronic components, thereby creating a lead frame in which multiple leads are integrated. It is used. In addition, in FIG. 2C, similarly to FIGS. 1B and 1C, a hole 7 is provided in the substrate 1 in advance, and the protrusion 9 of the lead 5 having a "T"-shaped tip is inserted into this hole 7.
It is soldered. Furthermore, Figure 2 D, E
In this method, a lead 5 having a concave tip is installed so that the recess 10 of the lead 5 grips the electrode part of the substrate 1, and is fixed by soldering in this state.

しかし、これらリードフレームは、第1図のリ
ードピンに比較して基板1への取付け力が強固で
容易であるが、各リードが一体化されているた
め、フアンクシヨントリミング特性チエツク前に
リードを切断しなければならない。また、第1図
および第2図の何れのものもリードピン、リード
フレームともに基板1よりリード5が突出してい
るため、半田ペースト印刷基板へリードを取付け
た後の加熱半田付け、洗浄、フアンクシヨントリ
ミング特性チエツクにおいて取扱いにくく、作業
性がきわめて悪いという問題があつた。
However, these lead frames have a stronger and easier attachment force to the substrate 1 than the lead pins shown in Fig. 1, but since each lead is integrated, it is necessary to attach the leads before checking the function trimming characteristics. Must be disconnected. In addition, in both the lead pins and lead frames in both Figures 1 and 2, the leads 5 protrude from the board 1, so the heat soldering, cleaning, and fusing after attaching the leads to the solder paste printed board are difficult. When checking the trimming characteristics, there was a problem that it was difficult to handle and the workability was extremely poor.

本発明は上記事情に鑑みてなされたもので、そ
の目的とするところは、基板のリードを取出す電
極部に金属片を半田付けし、この金属片にリード
を溶接することによつて、作業性の向上が図れ、
リードの確実かつ強固な取付けが可能となり、信
頼性が向上するとともに、量産性にも優れた混成
集積回路の製造方法を提供することにある。
The present invention has been made in view of the above circumstances, and its purpose is to improve workability by soldering a metal piece to the electrode part from which the lead of the board is taken out, and welding the lead to this metal piece. Improve your
It is an object of the present invention to provide a method for manufacturing a hybrid integrated circuit that enables reliable and strong attachment of leads, improves reliability, and is excellent in mass production.

以下、本発明の一実施例について図面を参照し
て説明する。
An embodiment of the present invention will be described below with reference to the drawings.

まず第3図Aに示すように、絶縁基板としての
セラミツク基板31の一方面上に厚膜ペースト印
刷により回路配線基板を形成し、この回路配線基
板の電子部品取付け部分に半田ペーストを印刷す
る。次に、この半田ペーストを設けた部分に能動
素子や受動素子、つまりICやトランジスタなど
の半導体素子32およびコンデンサ33などを半
田付けするとともに、これと同時に電極部34に
金属片35などを半田付けする。この金属片35
は、たとえばNiまたはSnメツキ処理した銅
(Cu)片または鉄(Fe)片などである。次にこの
半田付け工程終了後、洗浄、フアンクシヨントリ
ミング特性チエツクなどの工程を行う。次に第3
図BまたはCに示すように、上記金属片35にヘ
ツド36を有するリード37あるいはリードフレ
ーム38を、たとえばウエルドマシーンにより自
動溶接する。上記リード37およびリードフレー
ム38は、たとえば半田付け処理された銅
(Cu)線などである。
First, as shown in FIG. 3A, a circuit wiring board is formed by thick film paste printing on one side of a ceramic substrate 31 serving as an insulating substrate, and solder paste is printed on the electronic component mounting portion of this circuit wiring board. Next, active elements and passive elements, that is, semiconductor elements 32 such as ICs and transistors, capacitors 33, etc. are soldered to the parts provided with this solder paste, and at the same time, metal pieces 35 etc. are soldered to the electrode parts 34. do. This metal piece 35
is, for example, a copper (Cu) piece or an iron (Fe) piece plated with Ni or Sn. Next, after this soldering process is completed, processes such as cleaning and checking the function trimming characteristics are performed. Then the third
As shown in FIGS. B or C, a lead 37 or a lead frame 38 having a head 36 is automatically welded to the metal piece 35 using, for example, a welding machine. The leads 37 and lead frame 38 are, for example, soldered copper (Cu) wires.

このようにリードの取付けに際し、あらかじめ
金属片を取着し、この取着した金属片にリードを
溶接する本発明方法によれば次のような特徴があ
る。
As described above, the method of the present invention in which a metal piece is attached in advance and the lead is welded to the attached metal piece when attaching the lead has the following features.

リードを除き、金属片を含めたすべての部品
の自動マウンター化が可能となり、リードもウ
エルドマシーンにより自動溶接が可能であり、
よつて部品マウントにおける手作業が不用で量
産性に優れている。
With the exception of leads, all parts including metal pieces can be automatically mounted, and leads can also be automatically welded using a welding machine.
Therefore, there is no need for manual work in mounting parts, making it suitable for mass production.

半田付け、洗浄、フアンクシヨントリミン
グ、特性チエツク工程においては、基板にリー
ドが付いていないので作業が容易となり、工程
の移動も基板をマガジンなどに収納できるため
取扱いが容易となる。
Soldering, cleaning, function trimming, and characteristic checking processes are easier because there are no leads attached to the board, and handling is easier because the board can be stored in a magazine or the like during the process.

ウエルドマシーンによりリードを強固に溶接
するので確実に接続でき、半田付けより信頼性
が高い。
The leads are firmly welded using a welding machine, ensuring a secure connection and being more reliable than soldering.

従来のリードピン、リードフレームは、アウ
タリードの取出し方向により、基板リードを取
付けた後、フオーミングが必要となる場合があ
る。しかし本発明方法によれば、任意のリード
フオームを選ぶことができるので、基板にリー
ドを取付けた後のフオーミングを必要としな
い。
Conventional lead pins and lead frames may require forming after the substrate leads are attached, depending on the direction in which the outer leads are taken out. However, according to the method of the present invention, any lead form can be selected, so forming the leads after attaching them to the substrate is not necessary.

などの種々の効果が得られるものである。Various effects such as these can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図および第2図は従来の混成集積回路の製
造方法を説明するための図、第3図は本発明に係
る混成集積回路の製造方法の一実施例を説明する
ための図である。 31……セラミツク基板、32,33……電子
部品、34……電極部、35……金属片、36…
…ヘツド、37……リード、38……リードフレ
ーム。
1 and 2 are diagrams for explaining a conventional method for manufacturing a hybrid integrated circuit, and FIG. 3 is a diagram for explaining an embodiment of the method for manufacturing a hybrid integrated circuit according to the present invention. 31... Ceramic substrate, 32, 33... Electronic component, 34... Electrode section, 35... Metal piece, 36...
...Head, 37...Lead, 38...Lead frame.

Claims (1)

【特許請求の範囲】 1 混成集積回路基板の電極部にリードを取着す
るに際し、あらかじめ金属片を半田付けし、この
金属片にリードを溶接することを特徴とする混成
集積回路の製造方法。 2 金属片はNiまたはSnメツキ処理したCuまた
はFe板片である特許請求の範囲第1項記載の混
成集積回路の製造方法。 3 金属片は混成集積回路の電子部品と同一工程
で半田付けすることを特徴とする特許請求の範囲
第1項記載の混成集積回路の製造方法。
[Scope of Claims] 1. A method for manufacturing a hybrid integrated circuit, which comprises the steps of soldering a metal piece in advance and welding the lead to the metal piece when attaching the lead to the electrode portion of the hybrid integrated circuit board. 2. The method of manufacturing a hybrid integrated circuit according to claim 1, wherein the metal piece is a Cu or Fe plate plated with Ni or Sn. 3. The method of manufacturing a hybrid integrated circuit according to claim 1, wherein the metal piece is soldered in the same process as the electronic components of the hybrid integrated circuit.
JP56006673A 1981-01-20 1981-01-20 Manufacture of hybrid integrated circuit Granted JPS57121266A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56006673A JPS57121266A (en) 1981-01-20 1981-01-20 Manufacture of hybrid integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56006673A JPS57121266A (en) 1981-01-20 1981-01-20 Manufacture of hybrid integrated circuit

Publications (2)

Publication Number Publication Date
JPS57121266A JPS57121266A (en) 1982-07-28
JPS6259461B2 true JPS6259461B2 (en) 1987-12-11

Family

ID=11644883

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56006673A Granted JPS57121266A (en) 1981-01-20 1981-01-20 Manufacture of hybrid integrated circuit

Country Status (1)

Country Link
JP (1) JPS57121266A (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59114849A (en) * 1982-12-22 1984-07-03 Toshiba Corp Manufacture of hybrid integrated circuit
JPS63115234U (en) * 1987-01-21 1988-07-25

Also Published As

Publication number Publication date
JPS57121266A (en) 1982-07-28

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