JPH0625017Y2 - LSI package lead structure - Google Patents
LSI package lead structureInfo
- Publication number
- JPH0625017Y2 JPH0625017Y2 JP1987107963U JP10796387U JPH0625017Y2 JP H0625017 Y2 JPH0625017 Y2 JP H0625017Y2 JP 1987107963 U JP1987107963 U JP 1987107963U JP 10796387 U JP10796387 U JP 10796387U JP H0625017 Y2 JPH0625017 Y2 JP H0625017Y2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- plating
- lsi package
- solder
- pad
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000007747 plating Methods 0.000 claims description 26
- 229910000679 solder Inorganic materials 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 3
- 238000005476 soldering Methods 0.000 description 11
- 239000000463 material Substances 0.000 description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 239000006071 cream Substances 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 230000007774 longterm Effects 0.000 description 1
- 238000004381 surface treatment Methods 0.000 description 1
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【考案の詳細な説明】 産業上の利用分野 本考案は通信機，電子計算機等に使用されるＬＳＩパッ
ケージの実装に関し、特にリード構造に関する。DETAILED DESCRIPTION OF THE INVENTION Industrial Field of the Invention The present invention relates to mounting of an LSI package used in a communication device, an electronic computer or the like, and particularly to a lead structure.
従来の技術 装置の小型化に伴う電子部品の軽薄短小化と高く密度実
装への対応として、第３図に示すように電子回路等を構
成するプリント基板１の表面へＬＳＩパッケージ２′を
直接接続する実装構造（以下表面実装という）が採用さ
れ、第５図に示すようにＬＳＩパッケジ２′の基板３か
ら突出したリード４′をプリント基板１のパッド５の表
面に突き当て、半田６′にて接続して、ＬＳＩパッケー
ジ２′をプリント基板１上に実装している。2. Description of the Related Art As shown in FIG. 3, an LSI package 2'is directly connected to the surface of a printed circuit board 1 which constitutes an electronic circuit or the like, as shown in FIG. A mounting structure (hereinafter referred to as surface mounting) is adopted, and as shown in FIG. 5, the leads 4'protruding from the substrate 3 of the LSI package 2'abut against the surface of the pad 5 of the printed circuit board 1 and are soldered 6 '. Then, the LSI package 2 ′ is mounted on the printed circuit board 1.
第４図にリード構造の詳細を示しており、リード４′は
素材７の表面全体に第１めっき８，その上に第２めっき
９′を行なっている。普通、素材７は銅合金材料が使用
され、第１めっきは素材からの銅の拡散を防止するため
に施するもので、ニッケルめっきが行なわれる。次に第
２めっきは半田付け性向上のために施すもので、金めっ
き又は半田めっきが行なわれている。また、半田付け表
面実装であるため、普通クリーム半田がパッド５上に塗
布され、その上にＬＳＩパッケージ２′のリード４′を
接触させ、ペーパーリフロソルダリング（以下ＶＰＳと
いう）等の高温雰囲気で行なわれる。The details of the lead structure are shown in FIG. 4, and the lead 4'has the first plating 8 on the entire surface of the material 7 and the second plating 9'on it. Normally, the material 7 is a copper alloy material, and the first plating is performed to prevent the diffusion of copper from the material, and nickel plating is performed. Next, the second plating is performed to improve solderability, and gold plating or solder plating is performed. Further, since the surface mounting is soldering, cream solder is usually applied on the pad 5, and the lead 4'of the LSI package 2'is brought into contact with the pad 5 to be exposed to a high temperature atmosphere such as paper reflow soldering (hereinafter referred to as VPS). Done.
考案が解決しようとする問題点 ＶＰＳでの半田付けの場合、リード４′の熱容量がパッ
ド５の熱容量に比較して小さいため、リード４′の方が
温度上昇が速くなる。Problems to be Solved by the Invention In the case of VPS soldering, since the heat capacity of the lead 4'is smaller than the heat capacity of the pad 5, the temperature rise of the lead 4'is faster.
上述した従来のＬＳＩパッケージのリード構造は、リー
ドの前面に第２めっきを施していること、及びリードの
方が温度上昇が速いことから、半田付けの仕上り形状は
第５図６′のように半田がリード４′に取られ、パッド
５の部分に半田が残らないという状態になり、半田付け
不良が多発し、信頼性を損なうという欠点がある。In the lead structure of the conventional LSI package described above, the front surface of the lead is subjected to the second plating, and the temperature rise of the lead is faster, so the finished shape of the soldering is as shown in FIG. 5 '. The solder is taken by the lead 4 ', and the solder does not remain on the pad 5, resulting in frequent soldering failures and impairing reliability.
問題点を解決するための手段 上述の問題点に鑑み、本願考案のＬＳＩパッケージのリ
ード構造は、プリント基板上に表面実装されるＬＳＩパ
ッケージのパッケージ基板から突出したリードの構造に
おいて、このリードの全表面に施された、半田付け性の
悪い第１のめっき層と、この第１のめっき層上のリード
先端部のみに施され、実装時には前記プリント基板上の
パッドに半田付けされる、半田付け性の良い第２のめっ
き層とを有する。In view of the above-mentioned problems, the lead structure of the LSI package of the present invention has a structure in which the leads protruding from the package board of the LSI package surface-mounted on the printed board have all of the leads. Soldering, which is applied only to the surface of the first plating layer having poor solderability and the tip of the lead on the first plating layer, and is soldered to the pad on the printed circuit board during mounting. And a second plating layer having good properties.
作用 上述したように従来のリード構造では、半田付けの仕上
りが第５図のようになって、パッド５に半田がよくのら
ない欠点がある。本考案のリード構造は、半田付けの際
熱容量の小さいリードがまず温度上昇するが、半田は半
田付け性のよいめっきの施された先端部で融け、この部
分にとどまる。その後熱容量の大きいパッド５の部分が
温度上昇するに及んで、半田はパッド５上で融け広が
り、リードとパッドは半田で完全に接続される。Function As described above, the conventional lead structure has a drawback that the soldering finish is as shown in FIG. According to the lead structure of the present invention, the temperature of the lead having a small heat capacity first rises during soldering, but the solder melts at the plated tip portion having good solderability and stays in this portion. Thereafter, as the temperature of the pad 5 having a large heat capacity rises, the solder melts and spreads on the pad 5, and the lead and the pad are completely connected by the solder.
実施例 次に本考案の実施例について図面を参照して説明する。Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.
第１図は本考案の実施例の縦断面図である。リード４
は、素材７の全表面に半田付け性の悪い材料で第１めっ
き８を施し、その上に半田付け性の良い材料で第２めっ
き９を施して作られる。ただし第２めっき９は図に示す
ようにリードの先端部ｍのみに施される。普通、素材７
は銅合金材料が使用され、第１めっき８は素材からの銅
の拡散を防止するためにニッケルめっきが行なわれる。
次に第２めっき９は半田付け性向上のため金めっき又は
半田めっきが行なわれている。FIG. 1 is a vertical sectional view of an embodiment of the present invention. Lead 4
Is made by applying the first plating 8 on the entire surface of the material 7 with a material having poor solderability, and then applying the second plating 9 on the material with good solderability. However, the second plating 9 is applied only to the tips m of the leads as shown in the figure. Normally, material 7
Is a copper alloy material, and the first plating 8 is nickel plated to prevent the diffusion of copper from the material.
Next, the second plating 9 is plated with gold or solder to improve solderability.
このような表面処理が行なわれたリードをＶＰＳで半田
付けした場合の半田付け状態を第２図に示す。パッド５
上に塗布したクリーム半田はＶＰＳの高温雰囲気内で溶
融し、第１に温度上昇の速いリード側に引っぱられる。
しかし、溶融した半田は寸法ｌの所で止まる。寸法ｌは
第１図の寸法ｍに相当しており、第１めっき８はニッケ
ルめっきのため半田付け性が悪く半田が付きにくいため
である。次に溶融した半田はパッド側の温度が最適にな
ると、パッド側にも拡がり、良好な半田６のフィレット
が出来る。FIG. 2 shows a soldered state when the leads thus surface-treated are soldered by VPS. Pad 5
The cream solder applied on top is melted in the high temperature atmosphere of VPS, and is first pulled to the lead side where the temperature rises quickly.
However, the molten solder stops at dimension l. The dimension 1 corresponds to the dimension m in FIG. 1, because the first plating 8 is nickel-plated, so that the solderability is poor and the solder is hard to attach. Next, when the temperature of the pad side becomes optimum, the melted solder spreads also to the pad side, and a good fillet of the solder 6 is formed.
考案の効果 以上に説明したように、本考案によれば、ＬＳＩパッケ
ージのリードの表面処理を素材の前面に第１めっきであ
る半田の付きにくいニッケルめっきを施し、次にその上
にリードの先端部のみ第２めっきである半田の付きやす
い金めっき又は半田めっきを施すことにより、表面実装
におけるＶＰＳ半田付けの場合に、リードとパッド間に
温度上昇の差があったとしても良好な半田付けが出来、
半田接合部の長期的信頼性を向上させる効果がある。Advantageous Effects of Invention As described above, according to the present invention, the surface treatment of the leads of the LSI package is performed by applying the first plating, which is nickel plating that is difficult for soldering, to the tip of the leads. In the case of VPS soldering in surface mounting, good soldering can be achieved even if there is a difference in temperature rise between the lead and the pad, by performing gold plating or solder plating which is the second plating only on the part Done,
This has the effect of improving the long-term reliability of the solder joint.
第１図は本考案の実施例の縦断面図、第２図は本考案品
の使用状況を示す側面図、第３図は表面実装の全体を示
す斜視図、第４図は従来のリードの縦断面図、第５図は
その使用状況の側面図である。 １……プリント基板、２・２′……ＬＳＩパッケージ、
３……パッケージ基板、４，４′……リード、５……パ
ッド、６，６′……半田、７……素材、８……第１めっ
き、９，９′……第２めっき。FIG. 1 is a vertical cross-sectional view of an embodiment of the present invention, FIG. 2 is a side view showing the usage of the present invention, FIG. 3 is a perspective view showing the whole surface mounting, and FIG. 4 is a conventional lead. FIG. 5 is a side view of the state of use, which is a vertical sectional view. 1 ... Printed circuit board, 2.2 '... LSI package,
3 ... Package substrate, 4, 4 '... Lead, 5 ... Pad, 6, 6' ... Solder, 7 ... Material, 8 ... First plating, 9, 9 '... Second plating.
Claims (1)
ッケージのパッケージ基板から突出したリードの構造に
おいて、 このリードの全表面に施された、半田付け性の悪い第１
のめっき層と、 この第１のめっき層上のリード先端部のみに施され、実
装時には前記プリント基板上のパッドに半田付けされ
る、半田付け性の良い第２のめっき層とを有することを
特徴とするＬＳＩパッケージのリード構造。1. In a structure of a lead projecting from a package substrate of an LSI package which is surface-mounted on a printed circuit board, a first solder having poor solderability provided on the entire surface of the lead.
And a second plating layer having good solderability, which is applied only to the lead tips on the first plating layer and is soldered to the pads on the printed circuit board during mounting. Characteristic LSI package lead structure.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987107963U JPH0625017Y2 (en) | 1987-07-14 | 1987-07-14 | LSI package lead structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987107963U JPH0625017Y2 (en) | 1987-07-14 | 1987-07-14 | LSI package lead structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6413152U JPS6413152U (en) | 1989-01-24 |
| JPH0625017Y2 true JPH0625017Y2 (en) | 1994-06-29 |
Family
ID=31342853
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987107963U Expired - Lifetime JPH0625017Y2 (en) | 1987-07-14 | 1987-07-14 | LSI package lead structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0625017Y2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5041901A (en) * | 1989-05-10 | 1991-08-20 | Hitachi, Ltd. | Lead frame and semiconductor device using the same |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60154545A (en) * | 1984-01-23 | 1985-08-14 | Nec Corp | Semiconductor device |
-
1987
- 1987-07-14 JP JP1987107963U patent/JPH0625017Y2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6413152U (en) | 1989-01-24 |
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